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VME64x core
Commit f50d79fc authored by Tom Levens's avatar Tom Levens
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Add g_ASYNC_DTACK to verilog wrapper

parent a0ca042e
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hdl/rtl/vme64x_core_verilog.vhd
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......@@ -22,6 +22,7 @@ entity vme64x_core_verilog is
g_USER_CSR_EXT : natural := 0;
g_VME32 : natural := 1;
g_VME_2e : natural := 0;
g_ASYNC_DTACK : natural := 0;
g_WB_GRANULARITY : string(1 to 4);
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
......@@ -143,6 +144,7 @@ begin
g_USER_CSR_EXT => nat_to_bool(g_USER_CSR_EXT),
g_VME32 => nat_to_bool(g_VME32),
g_VME_2e => nat_to_bool(g_VME_2e),
g_ASYNC_DTACK => nat_to_bool(g_ASYNC_DTACK),
g_WB_GRANULARITY => string_to_wb_grn(g_WB_GRANULARITY),
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
......
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