Programming languages used in this repository
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VHDL
89.0 %
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SystemVerilog
7.03 %
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Makefile
1.95 %
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Stata
0.69 %
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Python
0.53 %
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Shell
0.45 %
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Verilog
0.35 %
Commit statistics for master Mar 31 - Jun 22
- Total: 455 commits
- Average per day: 0.1 commits
- Authors: 20
Commits per day of month
Commits per weekday
Commits per day hour (UTC)