xvme64x_core.vhd: workaround vivado 2020 bug.

Cf: https://support.xilinx.com/s/question/0D54U00005cVSUySAO/how-does-vivado-deal-with-vhdl-slice-assignment-with-opposite-directions?language=en_US&t=1664456754676

xvme64x_core.vhd: workaround vivado 2020 bug.
Cf: https://support.xilinx.com/s/question/0D54U00005cVSUySAO/how-does-vivado-deal-with-vhdl-slice-assignment-with-opposite-directions?language=en_US&t=1664456754676
a0ca042e · Tristan Gingold · ca57317a · a0ca042e
Commit a0ca042e authored Sep 30, 2022 by Tristan Gingold
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xvme64x_core.vhd hdl/rtl/xvme64x_core.vhd +3 -2

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--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
@@ -246,11 +246,12 @@ architecture rtl of xvme64x_core is
  signal s_vme_iackin_n         : std_logic;

  -- List of supported AM.
+  -- (use downto in the aggregate as a workaround Vivado 2020 bug).
  constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
-    (16#38# to 16#3f# => '1', --  A24
+    (16#3f# downto 16#38# => '1', --  A24
     16#2d# | 16#29#  => '1', --  A16
     16#20# => f_to_std_logic(g_VME32 and g_VME_2e),
-     16#08# to 16#0f# => f_to_std_logic(g_VME32), --  A32
+     16#0f# downto 16#08# => f_to_std_logic(g_VME32), --  A32
     others => '0');
 begin
  assert g_CLOCK_PERIOD > 0 report "g_CLOCK_PERIOD generic must be set"