vme_bus: precharge data.

d7c03c1b · Tristan Gingold · c4e8308e · d7c03c1b
Commit d7c03c1b authored Jan 24, 2020 by Tristan Gingold
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vme_bus.vhd hdl/rtl/vme_bus.vhd +29 -1

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--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -457,6 +457,21 @@ begin
            vme_dtack_oe_o   <= '1';
            vme_dtack_n_o    <= '1';

+            if s_transferType = MBLT
+              and s_MBLT_Data = '1'
+              and vme_idff_write_n = '1'
+              and s_wb_done = '1'
+            then
+              --  Next data read transfer.
+              --  Improve speed.
+              vme_odff_addr_dir  <= '1';
+              vme_odff_data_dir  <= '1';
+
+              vme_odff_addr <= data_reg(63 downto 33);
+              vme_odff_lword_n <= data_reg(32);
+              vme_odff_data    <= data_reg(31 downto 0);
+            end if;
+
            if vme_ds_n_i /= "11" then
              -- ANSI/VITA 1-1994 Table 4-1
              -- For interrupts ack, the handler MUST NOT drive WRITE* low
@@ -476,7 +491,20 @@ begin
                --  Improve speed.
                vme_odff_addr_dir  <= '1';
                vme_odff_data_dir  <= '1';
-                s_mainFSMstate <= DATA_TO_BUS;
+
+                if s_wb_done = '1' then
+                  --  Prefetch.
+                  s_wb_start <= '1';
+
+                  --  Already assert dtack (assume that data have been on the
+                  --  vme bus for at least one cycle).
+                  vme_dtack_oe_o   <= '1';
+                  vme_dtack_n_o    <= s_err;
+
+                  s_mainFSMstate <= DTACK_LOW;
+                else
+                  s_mainFSMstate <= DATA_TO_BUS;
+                end if;
              else
                s_mainFSMstate <= LATCH_DS;
              end if;