Commit 9388296e authored by Tristan Gingold's avatar Tristan Gingold

vme: preliminary support of 2eSST.

parent e02c9e0f
......@@ -106,10 +106,10 @@ package vme64x_pkg is
-- Not used, but for completness.
subtype t_xam_vec is std_logic_vector(7 downto 0);
constant c_AM_A32_2EVME : t_xam_vec := "00000001"; -- 0x01
constant c_AM_A64_2EVME : t_xam_vec := "00000010"; -- 0x02
constant c_AM_A32_2ESST : t_xam_vec := "00010001"; -- 0x11
constant c_AM_A64_2ESST : t_xam_vec := "00010010"; -- 0x12
constant c_XAM_A32_2EVME : t_xam_vec := "00000001"; -- 0x01
constant c_XAM_A64_2EVME : t_xam_vec := "00000010"; -- 0x02
constant c_XAM_A32_2ESST : t_xam_vec := "00010001"; -- 0x11
constant c_XAM_A64_2ESST : t_xam_vec := "00010010"; -- 0x12
------------------------------------------------------------------------------
-- Types
......
This diff is collapsed.
......@@ -63,6 +63,9 @@ entity xvme64x_core is
-- As a consequence, it uses a 16bit data wishbone bus.
g_VME32 : boolean := True;
-- If True, supports 2eSST.
g_VME_2e : boolean := True;
-- Address granularity on the WB bus. Value can be:
-- WORD: VME address bits 31:2 are translated to WB address bits 29:0,
-- the WB data represents bytes for VME address bits 1:0.
......@@ -237,6 +240,7 @@ architecture rtl of xvme64x_core is
constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
(16#38# to 16#3f# => '1', -- A24
16#2d# | 16#29# => '1', -- A16
16#20# => f_to_std_logic(g_VME32 and g_VME_2e),
16#08# to 16#0f# => f_to_std_logic(g_VME32), -- A32
others => '0');
begin
......@@ -320,6 +324,7 @@ begin
generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_VME32 => g_VME32,
g_VME_2E => g_VME_2E,
g_WB_GRANULARITY => g_WB_GRANULARITY,
g_WB_MODE => g_WB_MODE)
port map (
......
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