- 30 Apr, 2019 1 commit
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Dimitris Lampridis authored
Following up on 6c4dca2c, this commit fixes one issue related to resets and performs further reset and clock-domain crossing (CDC) cleanup. Important changes include: 1. Make sure that all dual async fifos are reset on both sides. This solves an issue with soft resets causing the host PC to hang. 2. Remove c_RST_ACTIVE constant to make the code simpler. 3. Remove reset from many signals (in particular from wide, data signals) that do not need to be reset. This helps with meeting timing wrt reset distribution. 4. Remove synchronizers from p2l deserializers, the SERDES outputs are already synced to the FPGA clock.
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- 26 Apr, 2019 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 12 Apr, 2019 1 commit
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Dimitris Lampridis authored
Important changes include: 1. Clear separation of resets per clock domain (with the exception of the wbgen-generated dma controller registers). 2. Conversion of all processes to use synchronous resets when the reset is synced with the clock of the process. 3. Use of standard synchronizers from general-cores when crossing clock-domains. Due to the change in processes to use sync resets, a lot of code has changed indentation. To this end, it might be useful to perform a case insensitive diff when studying the changes of this commit. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 14 Mar, 2019 1 commit
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Dimitris Lampridis authored
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- 13 Feb, 2019 1 commit
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Dimitris Lampridis authored
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- 30 Jan, 2019 1 commit
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Dimitris Lampridis authored
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- 29 Jan, 2019 1 commit
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Dimitris Lampridis authored
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- 28 Jan, 2019 1 commit
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Dimitris Lampridis authored
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- 23 Jan, 2019 6 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 29 Nov, 2018 4 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 26 Oct, 2018 1 commit
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Dimitris Lampridis authored
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- 16 Sep, 2018 1 commit
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Tomasz Wlostowski authored
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- 30 Aug, 2018 1 commit
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Tomasz Wlostowski authored
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- 13 Jun, 2018 1 commit
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Dimitris Lampridis authored
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- 08 Jun, 2018 1 commit
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Dimitris Lampridis authored
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- 26 Mar, 2018 1 commit
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Dimitris Lampridis authored
Fake merge (using 'ours' strategy) to make sure that commit 2710742b stays, since it is used by a BTrain-over-WR release. The commit itself is already rebased onto proposed_master as 9b9625bb.
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- 20 Mar, 2018 1 commit
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Dimitris Lampridis authored
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- 19 Mar, 2018 1 commit
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Dimitris Lampridis authored
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- 14 Dec, 2017 1 commit
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Dimitris Lampridis authored
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- 22 Aug, 2017 1 commit
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Tomasz Wlostowski authored
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- 27 Apr, 2017 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
sim: SV BFM assignment to port does not need MODPORT, greatly reduces number of warnings in Modelsim
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Dimitris Lampridis authored
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- 12 Apr, 2017 1 commit
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Dimitris Lampridis authored
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- 31 May, 2016 1 commit
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Tomasz Wlostowski authored
rtl/wbmaster32: fix a nasty freeze when accesses are very tightly spaced: CIDs should be also FIFOed!
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- 18 Mar, 2016 2 commits
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Javier D. Garcia-Lasheras authored
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Javier D. Garcia-Lasheras authored
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- 16 Sep, 2015 1 commit
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Grzegorz Daniluk authored
The sizes of to_wb and from_wb fifo were reduced in commit 4a430afa from 512 to 128 words. However, almost_full thresholds were still set to 500. As the result some of the requests were lost when fifo was full because this fact was never signaled to the gn4124 chip.
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- 01 Jul, 2015 1 commit
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Javier D. Garcia-Lasheras authored
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- 30 Jun, 2015 1 commit
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Tomasz Wlostowski authored
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