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Gennum GN4124 core
Commit 03197690 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: remove component declarations from top-level

parent 19e645d5
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hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
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......@@ -26,6 +26,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -134,56 +135,6 @@ end gn4124_core;
--==============================================================================
architecture rtl of gn4124_core is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_1_to_n_clk_pll_s2_diff
generic (
PLLD : integer := 1; -- Parameter to set division for PLL
PLLX : integer := 2; -- Parameter to set multiplier for PLL (2 for DDR)
CLKIN_PERIOD : real := 5.000; -- clock period (ns) of input clock on clkin_p
S : integer := 2; -- Parameter to set the serdes factor 1..8
BS : boolean := false; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic; -- Input from LVDS receiver pin
clkin_n : in std_logic; -- Input from LVDS receiver pin
reset : in std_logic; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0); -- Pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0); -- Alternate pattern that bitslip should search for
rxioclk : out std_logic; -- IO Clock network
rx_serdesstrobe : out std_logic; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic; -- Global clock
rx_pll_lckd : out std_logic; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0); -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end component serdes_1_to_n_clk_pll_s2_diff;
component gc_pulse_synchronizer is
port (
-- pulse input clock
clk_in_i : in std_logic;
-- pulse output clock
clk_out_i : in std_logic;
-- system reset (clk_in_i domain)
rst_n_i : in std_logic;
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o : out std_logic;
-- pulse input (clk_in_i domain)
d_p_i : in std_logic;
-- pulse output (clk_out_i domain)
q_p_o : out std_logic);
end component gc_pulse_synchronizer;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
......@@ -357,7 +308,7 @@ begin
------------------------------------------------------------------------------
-- Clock Input. Generate ioclocks and system clock via BUFPLL
------------------------------------------------------------------------------
cmp_clk_in : serdes_1_to_n_clk_pll_s2_diff
cmp_clk_in : entity work.serdes_1_to_n_clk_pll_s2_diff
generic map(
CLKIN_PERIOD => 5.000,
PLLD => 1,
......
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