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Gennum GN4124 core
Commit 254c6ef9 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: introduce example_tb testbench to demonstrate basic use of GN4124 BFM

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.gitmodules
View file @ 254c6ef9
[submodule "hdl/spec/ip_cores/general-cores"]
path = hdl/spec_test/ip_cores/general-cores
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
hdl/gn4124core/sim/example_tb/.gitignore 0 → 100644
View file @ 254c6ef9
work/
NullFile
Makefile
modelsim.ini
transcript*
*.wlf
hdl/gn4124core/sim/example_tb/Manifest.py 0 → 100644
View file @ 254c6ef9
sim_tool = "modelsim"
top_module = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
fetchto = "../../../ip_cores"
include_dirs = [
"../gn4124_bfm",
"../../../ip_cores/general-cores/sim/",
]
files = [
"main.sv",
]
modules = {
"local" : [
"../gn4124_bfm",
"../../rtl",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
hdl/gn4124core/sim/example_tb/README.md 0 → 100644
View file @ 254c6ef9
Introduction
============
This is a simple example testbench, to demonstrate how to use the SystemVerilog BFM of the GN4124 to perform simple accesses over wishbone.
The testbench simply connects the wishbone master of the GN4124 to its own DMA configuration wishbone slave.
Dependencies
============
To build this, you will need [hdl-make][1], using commit `968fa87` (or newer), as well as GNU Make.
The testbench also makes use of [general-cores][2], a dependency handled via git submodules.
To run it, you will need Modelsim/Questa. It has been tested with Questa 10.5c on Linux.
Build/Run Instrunctions
=======================
1. If not already done, pull all dependencies using `git submodule update --init` from within the gn4124 repository.
2. Run `hdlmake` from the example_tb directory.
3. Run `make` on the hdlmake-generated Makefile.
4. Run `vsim -c -do run.do`.
[1]: https://www.ohwr.org/projects/hdl-make/wiki
[2]: https://www.ohwr.org/projects/general-cores/wiki
hdl/gn4124core/sim/example_tb/main.sv 0 → 100644
View file @ 254c6ef9
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// GN4124 core for PCIe FMC carrier
// http://www.ohwr.org/projects/gn4124-core
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: This is a simple example testbench, to demonstrate how to use
// the SystemVerilog BFM of the GN4124 to perform simple accesses over wishbone.
//
// The testbench simply connects the wishbone master of the GN4124 to its own
// DMA configuration wishbone slave.
//
//------------------------------------------------------------------------------
// Copyright CERN 2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
import wishbone_pkg::*;
module main;
reg clk_125m = 0;
t_wishbone_master_in wb_in;
t_wishbone_master_out wb_out;
always #4ns clk_125m <= ~clk_125m;
IGN4124PCIMaster i_gn4124 ();
xwb_gn4124_core
DUT (
.rst_n_a_i (i_gn4124.rst_n),
.p2l_clk_p_i (i_gn4124.p2l_clk_p),
.p2l_clk_n_i (i_gn4124.p2l_clk_n),
.p2l_data_i (i_gn4124.p2l_data),
.p2l_dframe_i (i_gn4124.p2l_dframe),
.p2l_valid_i (i_gn4124.p2l_valid),
.p2l_rdy_o (i_gn4124.p2l_rdy),
.p_wr_req_i (i_gn4124.p_wr_req),
.p_wr_rdy_o (i_gn4124.p_wr_rdy),
.rx_error_o (i_gn4124.rx_error),
.vc_rdy_i (i_gn4124.vc_rdy),
.l2p_clk_p_o (i_gn4124.l2p_clk_p),
.l2p_clk_n_o (i_gn4124.l2p_clk_n),
.l2p_data_o (i_gn4124.l2p_data),
.l2p_dframe_o (i_gn4124.l2p_dframe),
.l2p_valid_o (i_gn4124.l2p_valid),
.l2p_edb_o (i_gn4124.l2p_edb),
.l2p_rdy_i (i_gn4124.l2p_rdy),
.l_wr_rdy_i (i_gn4124.l_wr_rdy),
.p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.tx_error_i (i_gn4124.tx_error),
.dma_irq_o (),
.irq_p_i (1'b0),
.irq_p_o (),
.status_o (),
.wb_master_clk_i (clk_125m),
.wb_master_rst_n_i (1'b1),
.wb_master_i (wb_in),
.wb_master_o (wb_out),
.wb_dma_cfg_clk_i (clk_125m),
.wb_dma_cfg_rst_n_i (1'b1),
.wb_dma_cfg_i (wb_out),
.wb_dma_cfg_o (wb_in),
.wb_dma_dat_clk_i (1'b0),
.wb_dma_dat_rst_n_i (1'b1),
.wb_dma_dat_i (),
.wb_dma_dat_o ()
);
CBusAccessor acc;
task reg_check(uint64_t addr, expected);
uint64_t val;
acc.read(addr, val);
if (val != expected)
begin
$display();
$display("Simulation FAILED");
$fatal(1, "Read-back error at address 0x%.2x. Expected 0x%.8x, got 0x%.8x",
addr, expected, val);
end
endtask // reg_check
initial begin
uint64_t addr, val;
@(posedge i_gn4124.ready);
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
@(posedge clk_125m);
reg_check('h0, 'h0);
acc.write('h10, 'hffacce55);
acc.write('h20, 'h1badcafe);
reg_check('h10, 'hffacce55);
reg_check('h20, 'h1badcafe);
for (addr = 'h00; addr <= 'h20; addr += 4)
begin
acc.read(addr, val);
$display("0x%.2x: 0x%.8x", addr, val);
end
$display();
$display("Simulation PASSED");
$finish;
end
endmodule // main
hdl/gn4124core/sim/example_tb/run.do 0 → 100644
View file @ 254c6ef9
vsim -quiet -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
hdl/gn4124core/sim/gn4124_bfm/Manifest.py
View file @ 254c6ef9
files = ["mem_model.vhd", "textutil.vhd", "gn412x_bfm.vhd", "util.vhd"]
files = [
"mem_model.vhd",
"textutil.vhd",
"gn412x_bfm.vhd",
"util.vhd",
]
general-cores @ 39c86c8e
Subproject commit 39c86c8ed49607b34d02d0df2de624ec77d222fd
general-cores @ 0545c25b
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
hdl/spec_test/sim/Manifest.py
View file @ 254c6ef9
......@@ -20,4 +20,4 @@ modules = {
],
}
fetchto = "../ip_cores"
fetchto = "../../ip_cores"
hdl/spec_test/syn/Manifest.py
View file @ 254c6ef9
......@@ -23,5 +23,5 @@ modules = {
],
}
fetchto = "../ip_cores"
fetchto = "../../ip_cores"
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