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Gennum GN4124 core
Commit 53f5b0e3 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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update top-level test module

parent dae10403
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Showing with 5 additions and 7 deletions
hdl/spec/rtl/spec_gn4124_test.vhd
View file @ 53f5b0e3
......@@ -206,7 +206,6 @@ architecture rtl of spec_gn4124_test is
signal wbm_stall : std_logic;
signal wbm_err : std_logic;
signal wbm_rty : std_logic;
signal wbm_int : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
......@@ -231,7 +230,6 @@ architecture rtl of spec_gn4124_test is
signal dma_stall : std_logic;
signal dma_err : std_logic;
signal dma_rty : std_logic;
signal dma_int : std_logic;
signal ram_we : std_logic;
-- Interrupts stuff
......@@ -359,7 +357,6 @@ begin
csr_stall_i => wbm_stall,
csr_err_i => wbm_err,
csr_rty_i => wbm_rty,
csr_int_i => wbm_int,
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
......@@ -374,8 +371,7 @@ begin
dma_ack_i => dma_ack,
dma_stall_i => dma_stall,
dma_err_i => dma_err,
dma_rty_i => dma_rty,
dma_int_i => dma_int
dma_rty_i => dma_rty
);
------------------------------------------------------------------------------
......@@ -422,7 +418,6 @@ begin
wbm_err <= '0';
wbm_rty <= '0';
wbm_int <= '0';
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
......@@ -513,7 +508,6 @@ begin
dma_err <= '0';
dma_rty <= '0';
dma_int <= '0';
------------------------------------------------------------------------------
......
hdl/spec/syn/.gitignore 0 → 100644
View file @ 53f5b0e3
*
!README
!.gitignore
!Manifest.py
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