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G
Gennum GN4124 core
Commit d434b7b6 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Upgrade hdlmake support in the SPEC syn demo

parent 7082c583
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Showing with 7 additions and 7 deletions
hdl/spec/syn/Manifest.py
View file @ d434b7b6
......@@ -6,6 +6,7 @@ syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_gn4124_test"
syn_project = "spec_gn4124_test.xise"
syn_tool = "ise"
files = ["../spec_gn4124_test.ucf",
"../ip_cores/l2p_fifo.ngc"]
......@@ -13,7 +14,7 @@ files = ["../spec_gn4124_test.ucf",
modules = { "local" : ["../rtl",
"../../common/rtl",
"../../gn4124core/rtl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::master"}
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master"}
fetchto = "../ip_cores"
hdl/spec/syn/README
View file @ d434b7b6
This example project was last tested on January 31st 2014,
using hdlmake (isyp branch, sha 6b7aa78e37cdd9b60b227834ad4ef307d242ed1b).
This example project was last tested on March 18st 2016,
using hdlmake (develop branch).
A binary of the generated gateware (spec_gn4124_test.bin) is stored in the
files section of the project:
......@@ -7,9 +7,8 @@ http://www.ohwr.org/projects/gn4124-core/files
Procedure to generate the gateware binary:
$ cd <gn4124 core dir>/hdl/spec/syn/
$ hdlmake -f
$ hdlmake --ise-proj
$ hdlmake --make-ise
$ hdlmake fetch
$ hdlmake
$ make
Memory map:
......@@ -25,4 +24,4 @@ Memory map:
0 : Not connected internally, can be used to perform r/w
4 : Not connected internally, can be used to perform r/w
8 : Not connected internally, can be used to perform r/w
C : Bits 0 and 1 connected to SPEC front-panel LEDs (1=LED ON)
\ No newline at end of file
C : Bits 0 and 1 connected to SPEC front-panel LEDs (1=LED ON)
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