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Gennum GN4124 core
Commit f667d8f8 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: eliminate last coregen fifo, switch to general-cores

parent 7f0b283b
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hdl/gn4124core/rtl/Manifest.py
View file @ f667d8f8
......@@ -8,11 +8,6 @@ files = [
"wbmaster32.vhd",
]
if action == "simulation":
files.append("../../spec_test/ip_cores/l2p_fifo.vhd")
elif action == "synthesis":
files.append("../../spec_test/ip_cores/l2p_fifo.ngc")
modules = {
"local" : [
"spartan6",
......
hdl/gn4124core/rtl/l2p_dma_master.vhd
View file @ f667d8f8
......@@ -81,26 +81,6 @@ entity l2p_dma_master is
end l2p_dma_master;
architecture behavioral of l2p_dma_master is
---------------------
-- Components
---------------------
component l2p_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic
);
end component;
---------------------
-- Constants
......@@ -113,7 +93,7 @@ architecture behavioral of l2p_dma_master is
---------------------
-- Signals
---------------------
signal fifo_rst : std_logic;
signal fifo_rst_n : std_logic;
signal fifo_rst_t : std_logic;
-- Data FIFO
......@@ -174,7 +154,7 @@ architecture behavioral of l2p_dma_master is
signal wb_cyc_cnt : unsigned(12 downto 0);
begin
fifo_rst <= not rst_n_i or fifo_rst_t;
fifo_rst_n <= rst_n_i and (not fifo_rst_t);
ldm_arb_valid_o <= ldm_arb_valid;
ldm_arb_data_o <= ldm_arb_data_l;
......@@ -565,41 +545,47 @@ begin
end if;
end if;
end process data_rec_proc;
---------------------
-- FIFOs
---------------------
cmp_addr_fifo : l2p_fifo
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => l2p_dma_clk_i,
din => addr_fifo_din,
wr_en => addr_fifo_wr,
rd_en => addr_fifo_rd,
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(c_ADDR_FIFO_FULL_THRES, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(c_ADDR_FIFO_FULL_THRES-50, 10)),
dout => addr_fifo_dout,
full => open,
empty => addr_fifo_empty,
valid => open,
prog_full => addr_fifo_full
);
cmp_data_fifo : l2p_fifo
port map (
rst => fifo_rst,
wr_clk => l2p_dma_clk_i,
rd_clk => clk_i,
din => data_fifo_din,
wr_en => data_fifo_wr,
rd_en => data_fifo_rd,
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(c_DATA_FIFO_FULL_THRES, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(c_DATA_FIFO_FULL_THRES-50, 10)),
dout => data_fifo_dout,
full => open,
empty => data_fifo_empty,
valid => open,
prog_full => data_fifo_full
);
cmp_addr_fifo: generic_async_fifo
generic map (
g_data_width => 32,
g_size => 1024,
g_with_wr_full => false,
g_with_wr_almost_full => true,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_ADDR_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => addr_fifo_din,
we_i => addr_fifo_wr,
wr_almost_full_o => addr_fifo_full,
clk_rd_i => l2p_dma_clk_i,
q_o => addr_fifo_dout,
rd_i => addr_fifo_rd,
rd_empty_o => addr_fifo_empty);
cmp_data_fifo: generic_async_fifo
generic map (
g_data_width => 32,
g_size => 1024,
g_with_wr_full => false,
g_with_wr_almost_full => true,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_DATA_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => l2p_dma_clk_i,
d_i => data_fifo_din,
we_i => data_fifo_wr,
wr_almost_full_o => data_fifo_full,
clk_rd_i => clk_i,
q_o => data_fifo_dout,
rd_i => data_fifo_rd,
rd_empty_o => data_fifo_empty);
end behavioral;
general-cores @ 0545c25b
Subproject commit fa0d99ed43f1a46fef912eccb9874dae8554a371
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
hdl/spec_test/ip_cores/l2p_fifo.ngc deleted 100644 → 0
View file @ 7f0b283b
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec_test/ip_cores/l2p_fifo.vhd deleted 100644 → 0
View file @ 7f0b283b
This diff is collapsed.
hdl/spec_test/ip_cores/l2p_fifo.xco deleted 100644 → 0
View file @ 7f0b283b
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Mon Jun 16 08:55:36 2014
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=l2p_fifo
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=32
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=32
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: a450c04f
hdl/spec_test/sim/.gitignore
View file @ f667d8f8
......@@ -2,5 +2,5 @@ work/
Makefile
modelsim.ini
transcript*
*.wlf
vsim.wlf
usc.lst
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