hdl: add keep attributes to clock signals to be able to create timing constraints on them

10cd74b0 · Dimitris Lampridis · 03197690 · 10cd74b0
Commit 10cd74b0 authored Nov 29, 2018 by Dimitris Lampridis
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gn4124_core.vhd hdl/gn4124core/rtl/spartan6/gn4124_core.vhd +4 -0

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--- a/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
@@ -145,6 +145,10 @@ architecture rtl of gn4124_core is
  signal serdes_strobe  : std_logic;
  signal p2l_pll_locked : std_logic;

+  attribute keep                 : string;
+  attribute keep of sys_clk : signal is "TRUE";
+  attribute keep of io_clk  : signal is "TRUE";
+
  -- Reset for all clk_p logic
  signal rst_reg : std_logic;
  signal rst_reg_d : std_logic;