Note: To avoid host hang in case of access to un-mapped address
      and user logic not asserting ERR signal.

core: Add err, rty and int signals to the wishbone masters interfaces. Terminate wb cycle in case of err on csr wb bus.

Note: The wb crossbar asserts err in case of access to un-mapped address.
      Therefore to avoid host hang in case of access to un-mapped address,
      the wb cycle is terminated (and returns 0xFFFFFFFF in case of read cycle).

tx_error acts as the abort signal.

git-svn-id: http://svn.ohwr.org/gn4124-core//trunk@195 490a43f0-0bf3-4ba5-ab97-d7cdfc39d34c

Fix bug in P2L DMA master, was decrementing data counter even if data where not from a completion with ID frame.

Bug fix in L2P DMA FSM, was checking l_wr_rdy only before sendind the 1st packet and not for the next packets in case of data split into several packets. Long DMA were causing the GN4124 chip to crash.