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Commit 383a8a24 authored by Matthieu Cattin's avatar Matthieu Cattin
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Replace Xilinx FIFOs by generic ones from ohwr general-cores.

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hdl/gn4124core/rtl/Manifest.py
+ 4
− 2
View file @ 383a8a24
files = ["dma_controller.vhd",
"dma_controller_wb_slave.vhd",
"gn4124_core_pkg.vhd",
"l2p_arbiter.vhd",
"l2p_dma_master.vhd",
"p2l_decode32.vhd",
"p2l_dma_master.vhd",
"wbmaster32.vhd"]
modules = { "local" : "spartan6" }
modules = { "local" : "spartan6",
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git" }
fetchto = "ip_cores"
hdl/gn4124core/rtl/l2p_dma_master.vhd
+ 94
− 38
View file @ 383a8a24
......@@ -16,10 +16,11 @@
-- description: Provides a pipelined Wishbone interface to performs DMA
-- transfers from local application to PCI express host.
--
-- dependencies: Xilinx FIFOs (fifo_32x512.xco)
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- last changes: see svn log
-- last changes: 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support
--------------------------------------------------------------------------------
......@@ -28,6 +29,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
entity l2p_dma_master is
......@@ -95,9 +97,9 @@ architecture behaviour of l2p_dma_master is
-- c_L2P_MAX_PAYLOAD is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_L2P_MAX_PAYLOAD values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_L2P_MAX_PAYLOAD : unsigned(10 downto 0) := to_unsigned(32, 11); -- in 32-bit words
constant c_ADDR_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_DATA_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_L2P_MAX_PAYLOAD : unsigned(10 downto 0) := to_unsigned(32, 11); -- in 32-bit words
constant c_ADDR_FIFO_FULL_THRES : integer := 500;
constant c_DATA_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
......@@ -108,7 +110,7 @@ architecture behaviour of l2p_dma_master is
signal dma_length_cnt : unsigned(29 downto 0);
-- Sync FIFOs
signal fifo_rst : std_logic;
signal fifo_rst_n : std_logic;
signal addr_fifo_rd : std_logic;
signal addr_fifo_valid : std_logic;
signal addr_fifo_empty : std_logic;
......@@ -158,11 +160,11 @@ begin
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst <= not(rst_n_i);
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst <= rst_n_i;
fifo_rst_n <= not(rst_n_i);
end generate;
------------------------------------------------------------------------------
......@@ -359,7 +361,7 @@ begin
end if;
else
-- arbiter or GN4124 not ready to receive a new packet
ldm_arb_valid_o <= '0';
ldm_arb_valid_o <= '0';
end if;
when L2P_ADDR_H =>
......@@ -486,37 +488,91 @@ begin
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
cmp_addr_fifo : fifo_32x512
cmp_addr_fifo : generic_async_fifo
generic map (
g_data_width => 32,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_ADDR_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => l2p_dma_clk_i,
din => addr_fifo_din,
wr_en => addr_fifo_wr,
rd_en => addr_fifo_rd,
prog_full_thresh_assert => c_ADDR_FIFO_FULL_THRES,
prog_full_thresh_negate => c_ADDR_FIFO_FULL_THRES,
dout => addr_fifo_dout,
full => open,
empty => addr_fifo_empty,
valid => addr_fifo_valid,
prog_full => addr_fifo_full);
cmp_data_fifo : fifo_32x512
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => addr_fifo_din,
we_i => addr_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => addr_fifo_full,
wr_count_o => open,
clk_rd_i => l2p_dma_clk_i,
q_o => addr_fifo_dout,
rd_i => addr_fifo_rd,
rd_empty_o => addr_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_addr_fifo_valid : process(l2p_dma_clk_i)
begin
if rising_edge(l2p_dma_clk_i) then
addr_fifo_valid <= addr_fifo_rd and (not addr_fifo_empty);
end if;
end process;
cmp_data_fifo : generic_async_fifo
generic map (
g_data_width => 32,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_DATA_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => l2p_dma_clk_i,
rd_clk => clk_i,
din => data_fifo_din,
wr_en => data_fifo_wr,
rd_en => data_fifo_rd,
prog_full_thresh_assert => c_DATA_FIFO_FULL_THRES,
prog_full_thresh_negate => c_DATA_FIFO_FULL_THRES,
dout => data_fifo_dout,
full => open,
empty => data_fifo_empty,
valid => data_fifo_valid,
prog_full => data_fifo_full);
rst_n_i => fifo_rst_n,
clk_wr_i => l2p_dma_clk_i,
d_i => data_fifo_din,
we_i => data_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => data_fifo_full,
wr_count_o => open,
clk_rd_i => clk_i,
q_o => data_fifo_dout,
rd_i => data_fifo_rd,
rd_empty_o => data_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_data_fifo_valid : process(clk_i)
begin
if rising_edge(clk_i) then
data_fifo_valid <= data_fifo_rd and (not data_fifo_empty);
end if;
end process;
data_fifo_din <= l2p_dma_dat_i;
-- latch data when receiving ack and the cycle has been initiated by this master
......
hdl/gn4124core/rtl/p2l_dma_master.vhd
+ 50
− 21
View file @ 383a8a24
......@@ -17,10 +17,11 @@
-- transfers from PCI express host to local application.
-- This entity is also used to catch the next item in chained DMA.
--
-- dependencies:
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- last changes: see svn log
-- last changes: 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
......@@ -29,6 +30,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
entity p2l_dma_master is
......@@ -123,8 +125,8 @@ architecture behaviour of p2l_dma_master is
-- c_MAX_READ_REQ_SIZE is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_MAX_READ_REQ_SIZE values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
......@@ -151,7 +153,7 @@ architecture behaviour of p2l_dma_master is
signal target_addr_cnt : unsigned(29 downto 0);
-- sync fifo
signal fifo_rst : std_logic;
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
......@@ -182,11 +184,11 @@ begin
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst <= not(rst_n_i);
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst <= rst_n_i;
fifo_rst_n <= not(rst_n_i);
end generate;
-- Errors to DMA controller
......@@ -490,21 +492,48 @@ begin
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
cmp_to_wb_fifo : fifo_64x512
cmp_to_wb_fifo : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => p2l_dma_clk_i,
din => to_wb_fifo_din,
wr_en => to_wb_fifo_wr,
rd_en => to_wb_fifo_rd,
prog_full_thresh_assert => c_TO_WB_FIFO_FULL_THRES,
prog_full_thresh_negate => c_TO_WB_FIFO_FULL_THRES,
dout => to_wb_fifo_dout,
full => open,
empty => to_wb_fifo_empty,
valid => to_wb_fifo_valid,
prog_full => to_wb_fifo_full);
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => p2l_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_fifo_valid : process(p2l_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
to_wb_fifo_valid <= to_wb_fifo_rd and (not to_wb_fifo_empty);
end if;
end process;
-- pause transfer from GN4124 if fifo is (almost) full
p2l_rdy_o <= not(to_wb_fifo_full);
......
hdl/gn4124core/rtl/wbmaster32.vhd
+ 77
− 34
View file @ 383a8a24
......@@ -16,12 +16,14 @@
-- description: Provides a Wishbone interface for single read and write
-- control and status registers
--
-- dependencies: Xilinx FIFOs (fifo_32x512.xco, fifo_64x512.xco)
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- last changes: 27-09-2010 (mcattin) Split wishbone and gn4124 clock domains
-- All signals crossing the clock domains are now going through fifos.
-- Dead times optimisation in packet generator.
-- 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
......@@ -30,6 +32,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
entity wbmaster32 is
......@@ -102,15 +105,15 @@ architecture behaviour of wbmaster32 is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
constant c_TO_WB_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_FROM_WB_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
constant c_FROM_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Sync fifos
signal fifo_rst : std_logic;
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
......@@ -166,11 +169,11 @@ begin
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst <= not(rst_n_i);
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst <= rst_n_i;
fifo_rst_n <= not(rst_n_i);
end generate;
------------------------------------------------------------------------------
......@@ -299,42 +302,82 @@ begin
-----------------------------------------------------------------------------
-- fifo for PCIe to WB transfer
cmp_fifo_to_wb : fifo_64x512
cmp_fifo_to_wb : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => wb_clk_i,
din => to_wb_fifo_din,
wr_en => to_wb_fifo_wr,
rd_en => to_wb_fifo_rd,
prog_full_thresh_assert => c_TO_WB_FIFO_FULL_THRES,
prog_full_thresh_negate => c_TO_WB_FIFO_FULL_THRES,
dout => to_wb_fifo_dout,
full => open,
empty => to_wb_fifo_empty,
valid => open,
prog_full => to_wb_fifo_full);
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => wb_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
to_wb_fifo_rw <= to_wb_fifo_dout(63);
to_wb_fifo_addr <= to_wb_fifo_dout(62 downto 32); -- 31-bit
to_wb_fifo_data <= to_wb_fifo_dout(31 downto 0); -- 32-bit
-- fifo for WB to PCIe transfer
cmp_from_wb_fifo : fifo_32x512
cmp_from_wb_fifo : generic_async_fifo
generic map (
g_data_width => 32,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_FROM_WB_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => wb_clk_i,
rd_clk => clk_i,
din => from_wb_fifo_din,
wr_en => from_wb_fifo_wr,
rd_en => from_wb_fifo_rd,
prog_full_thresh_assert => c_FROM_WB_FIFO_FULL_THRES,
prog_full_thresh_negate => c_FROM_WB_FIFO_FULL_THRES,
dout => from_wb_fifo_dout,
full => open,
empty => from_wb_fifo_empty,
valid => open,
prog_full => from_wb_fifo_full);
rst_n_i => fifo_rst_n,
clk_wr_i => wb_clk_i,
d_i => from_wb_fifo_din,
we_i => from_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => from_wb_fifo_full,
wr_count_o => open,
clk_rd_i => clk_i,
q_o => from_wb_fifo_dout,
rd_i => from_wb_fifo_rd,
rd_empty_o => from_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
-----------------------------------------------------------------------------
-- Wishbone master FSM
......
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