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Commit 6269b8f0 authored by Matthieu Cattin's avatar Matthieu Cattin
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Test with IODDR2 and BUFIO2.

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hdl/gn4124core/rtl/Manifest.py
+ 1
− 1
View file @ 6269b8f0
......@@ -6,7 +6,7 @@ files = ["dma_controller.vhd",
"p2l_dma_master.vhd",
"wbmaster32.vhd"]
modules = { "local" : "spartan6",
modules = { "local" : "spartan3",
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git" }
fetchto = "../ip_cores"
......
hdl/gn4124core/rtl/spartan3/Manifest.py
+ 1
− 1
View file @ 6269b8f0
files = ["gn4124_core.vhd",
"gn4124_core_private_pkg.vhd",
"gn4124_core_pkg.vhd",
"l2p_ser.vhd",
"p2l_des.vhd"]
hdl/gn4124core/rtl/spartan3/gn4124_core.vhd
+ 168
− 69
View file @ 6269b8f0
......@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: Gn4124 core main block (gn4124-core.vhd)
-- unit name: Gn4124 core main block (gn4124_core.vhd)
--
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
......@@ -50,8 +50,14 @@ entity gn4124_core is
port
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
---------------------------------------------------------
-- P2L Direction
......@@ -130,13 +136,19 @@ architecture rtl of gn4124_core is
------------------------------------------------------------------------------
-- Clock
signal clk_p : std_logic;
signal clk_n : std_logic;
signal clk_p_buf : std_logic;
signal clk_n_buf : std_logic;
signal clk_p : std_logic;
signal clk_n : std_logic;
signal clk_p_buf : std_logic;
signal clk_n_buf : std_logic;
signal clk_p_io : std_logic;
signal clk_n_io : std_logic;
signal clk_sys_buf : std_logic;
signal clk_sys : std_logic;
signal clk_sys_n_buf : std_logic;
signal clk_sys_n : std_logic;
-- Reset for all clk_p logic
signal rst_reg : std_logic;
signal rst_n : std_logic;
signal rst_reg : std_logic;
signal rst_n : std_logic;
-------------------------------------------------------------
-- P2L DataPath (from deserializer to packet decoder)
......@@ -177,12 +189,18 @@ architecture rtl of gn4124_core is
signal arb_ser_data : std_logic_vector(31 downto 0);
-- Local bus control
signal l_wr_rdy_t : std_logic_vector(1 downto 0);
signal l_wr_rdy : std_logic_vector(1 downto 0);
signal p_rd_d_rdy_t : std_logic_vector(1 downto 0);
signal p_rd_d_rdy : std_logic_vector(1 downto 0);
signal l2p_rdy_t : std_logic;
signal l2p_rdy : std_logic;
signal l_wr_rdy_t : std_logic_vector(1 downto 0);
signal l_wr_rdy_t2 : std_logic_vector(1 downto 0);
signal l_wr_rdy : std_logic_vector(1 downto 0);
signal p_rd_d_rdy_t : std_logic_vector(1 downto 0);
signal p_rd_d_rdy_t2 : std_logic_vector(1 downto 0);
signal p_rd_d_rdy : std_logic_vector(1 downto 0);
signal l2p_rdy_t : std_logic;
signal l2p_rdy_t2 : std_logic;
signal l2p_rdy : std_logic;
signal l2p_edb : std_logic;
signal l2p_edb_t : std_logic;
signal l2p_edb_t2 : std_logic;
-------------------------------------------------------------
-- CSR wishbone master to arbiter
......@@ -283,40 +301,100 @@ architecture rtl of gn4124_core is
--==============================================================================
begin
-----------------------------------------------------------------------------
-- Unused entity port (kept for compatibility)
-----------------------------------------------------------------------------
debug_o <= (others => '0');
p2l_pll_locked <= '0';
-----------------------------------------------------------------------------
-- The Internal Core Clock is Derived from the P2L_CLK
-----------------------------------------------------------------------------
CLK_ibuf : IBUFGDS
port map(
I => p2l_clk_p_i,
IB => p2l_clk_n_i,
O => clk_p_buf);
CLK_bufg : BUFG
port map(
I => clk_p_buf,
O => clk_p);
CLKn_ibuf : IBUFGDS
port map(
I => p2l_clk_n_i,
IB => p2l_clk_p_i,
O => clk_n_buf);
CLKn_bufg : BUFG
port map(
I => clk_n_buf,
O => clk_n);
gen_clk_s3 : if g_IS_SPARTAN6 = false generate
CLK_ibuf : IBUFGDS
port map(
I => p2l_clk_p_i,
IB => p2l_clk_n_i,
O => clk_p_buf);
CLK_bufg : BUFG
port map(
I => clk_p_buf,
O => clk_p_io);
CLKn_ibuf : IBUFGDS
port map(
I => p2l_clk_n_i,
IB => p2l_clk_p_i,
O => clk_n_buf);
CLKn_bufg : BUFG
port map(
I => clk_n_buf,
O => clk_n_io);
clk_sys <= clk_p_io;
clk_sys_n <= clk_n_io;
end generate gen_clk_s3;
gen_clk_s6 : if g_IS_SPARTAN6 = true generate
clk_p_ibuf : IBUFGDS
port map (
I => p2l_clk_p_i,
IB => p2l_clk_n_i,
O => clk_p_buf
);
clk_p_bufio2 : BUFIO2
generic map (
DIVIDE => 2,
DIVIDE_BYPASS => true, -- DIVCLK output sourced from Divider (FALSE) or from I input (TRUE).
I_INVERT => false,
USE_DOUBLER => true
)
port map (
DIVCLK => clk_sys_buf,
IOCLK => clk_p_io,
SERDESSTROBE => open,
I => clk_p_buf
);
clk_n_bufio2 : BUFIO2
generic map (
DIVIDE => 2,
DIVIDE_BYPASS => true, -- DIVCLK output sourced from Divider (FALSE) or from I input (TRUE).
I_INVERT => true,
USE_DOUBLER => true
)
port map (
DIVCLK => clk_sys_n_buf,
IOCLK => clk_n_io,
SERDESSTROBE => open,
I => clk_p_buf
);
clk_sys_buf : BUFG
port map (
O => clk_sys,
I => clk_sys_buf
);
clk_sys_n_buf : BUFG
port map (
O => clk_sys_n,
I => clk_sys_n_buf
);
end generate gen_clk_s6;
------------------------------------------------------------------------------
-- Reset aligned to core clock
------------------------------------------------------------------------------
p_core_rst : process (clk_p, rst_n_a_i)
p_core_rst : process (clk_sys, rst_n_a_i)
begin
if rst_n_a_i = c_RST_ACTIVE then
rst_reg <= c_RST_ACTIVE;
elsif rising_edge(clk_p) then
elsif rising_edge(clk_sys) then
rst_reg <= not(c_RST_ACTIVE);
end if;
end process p_core_rst;
......@@ -354,9 +432,11 @@ begin
(
---------------------------------------------------------
-- Raw unprocessed reset from the GN412x
rst_n_i => rst_n,
clk_p_i => clk_p,
clk_n_i => clk_n,
rst_n_i => rst_n,
clk_sys_i => clk_sys,
clk_sys_n_i => clk_sys_n,
clk_p_i => clk_p_io,
clk_n_i => clk_n_io,
---------------------------------------------------------
-- P2L Clock Domain
......@@ -389,7 +469,7 @@ begin
(
---------------------------------------------------------
-- Clock/Reset
clk_i => clk_p,
clk_i => clk_sys,
rst_n_i => rst_n,
---------------------------------------------------------
......@@ -442,7 +522,7 @@ begin
(
---------------------------------------------------------
-- Clock/Reset
clk_i => clk_p,
clk_i => clk_sys,
rst_n_i => rst_n,
---------------------------------------------------------
......@@ -507,7 +587,7 @@ begin
cmp_dma_controller : dma_controller
port map
(
clk_i => clk_p,
clk_i => clk_sys,
rst_n_i => rst_n,
dma_ctrl_irq_o => dma_irq_o,
......@@ -554,7 +634,7 @@ begin
cmp_l2p_dma_master : l2p_dma_master
port map
(
clk_i => clk_p,
clk_i => clk_sys,
rst_n_i => rst_n,
dma_ctrl_target_addr_i => dma_ctrl_carrier_addr,
......@@ -573,7 +653,7 @@ begin
ldm_arb_req_o => ldm_arb_req,
arb_ldm_gnt_i => arb_ldm_gnt,
l2p_edb_o => l2p_edb_o,
l2p_edb_o => l2p_edb,
l_wr_rdy_i => l_wr_rdy,
l2p_rdy_i => l2p_rdy,
......@@ -586,7 +666,8 @@ begin
l2p_dma_stb_o => l2p_dma_stb,
l2p_dma_we_o => l2p_dma_we,
l2p_dma_ack_i => l2p_dma_ack,
l2p_dma_stall_i => l2p_dma_stall
l2p_dma_stall_i => l2p_dma_stall,
p2l_dma_cyc_i => p2l_dma_cyc
);
-----------------------------------------------------------------------------
......@@ -595,7 +676,7 @@ begin
cmp_p2l_dma_master : p2l_dma_master
port map
(
clk_i => clk_p,
clk_i => clk_sys,
rst_n_i => rst_n,
dma_ctrl_carrier_addr_i => dma_ctrl_carrier_addr,
......@@ -639,6 +720,7 @@ begin
p2l_dma_we_o => p2l_dma_we,
p2l_dma_ack_i => p2l_dma_ack,
p2l_dma_stall_i => p2l_dma_stall,
l2p_dma_cyc_i => l2p_dma_cyc,
next_item_carrier_addr_o => next_item_carrier_addr,
next_item_host_addr_h_o => next_item_host_addr_h,
......@@ -669,12 +751,12 @@ begin
dma_stb_o <= p2l_dma_stb;
dma_we_o <= p2l_dma_we;
else
dma_adr_o <= (others => 'X');
dma_dat_o <= (others => 'X');
dma_sel_o <= (others => 'X');
dma_adr_o <= (others => '0');
dma_dat_o <= (others => '0');
dma_sel_o <= (others => '0');
dma_cyc_o <= '0';
dma_stb_o <= '0';
dma_we_o <= 'X';
dma_we_o <= '0';
end if;
end process p_dma_wb_mux;
......@@ -693,30 +775,45 @@ begin
-----------------------------------------------------------------------------
-- Resync GN412x L2P status signals
-----------------------------------------------------------------------------
p_l2p_status_sync : process (clk_p, rst_n)
p_l2p_status_sync : process (clk_sys, rst_n)
begin
if(rst_n = c_RST_ACTIVE) then
l_wr_rdy_t <= "00";
l_wr_rdy <= "00";
p_rd_d_rdy_t <= "00";
p_rd_d_rdy <= "00";
l2p_rdy_t <= '0';
l2p_rdy <= '0';
elsif rising_edge(clk_p) then
l_wr_rdy_t <= "00";
l_wr_rdy_t2 <= "00";
l_wr_rdy <= "00";
p_rd_d_rdy_t <= "00";
p_rd_d_rdy_t2 <= "00";
p_rd_d_rdy <= "00";
l2p_rdy_t <= '0';
l2p_rdy_t2 <= '0';
l2p_rdy <= '0';
l2p_edb_o <= '0';
l2p_edb_t <= '0';
l2p_edb_t2 <= '0';
elsif rising_edge(clk_sys) then
-- must be checked before l2p_dma_master issues a master write
l_wr_rdy_t <= l_wr_rdy_i;
l_wr_rdy <= l_wr_rdy_t;
l_wr_rdy_t <= l_wr_rdy_i;
l_wr_rdy_t2 <= l_wr_rdy_t;
l_wr_rdy <= l_wr_rdy_t2;
-- must be checked before wbmaster32 sends read completion with data
p_rd_d_rdy_t <= p_rd_d_rdy_i;
p_rd_d_rdy <= p_rd_d_rdy_t;
p_rd_d_rdy_t <= p_rd_d_rdy_i;
p_rd_d_rdy_t2 <= p_rd_d_rdy_t;
p_rd_d_rdy <= p_rd_d_rdy_t2;
-- when de-asserted, l2p_dma_master must stop sending data (de-assert l2p_valid) within 3 (or 7 ?) clock cycles
l2p_rdy_t <= l2p_rdy_i;
l2p_rdy <= l2p_rdy_t;
l2p_rdy_t <= l2p_rdy_i;
l2p_rdy_t2 <= l2p_rdy_t;
l2p_rdy <= l2p_rdy_t2;
--assert when packet badly ends (e.g. dma abort)
l2p_edb_t <= l2p_edb;
l2p_edb_t2 <= l2p_edb_t;
l2p_edb_o <= l2p_edb_t2;
end if;
end process p_l2p_status_sync;
-----------------------------------------------------------------------------
-- L2P arbiter, arbitrates access to GN4124
-----------------------------------------------------------------------------
......@@ -725,7 +822,7 @@ begin
(
---------------------------------------------------------
-- Clock/Reset
clk_i => clk_p,
clk_i => clk_sys,
rst_n_i => rst_n,
---------------------------------------------------------
......@@ -772,9 +869,11 @@ begin
(
---------------------------------------------------------
-- clk_p Clock Domain Inputs
clk_p_i => clk_p,
clk_n_i => clk_n,
rst_n_i => rst_n,
clk_sys_i => clk_sys,
clk_sys_n_i => clk_sys_n,
clk_p_i => clk_p_io,
clk_n_i => clk_n_io,
rst_n_i => rst_n,
---------------------------------------------------------
-- DeSerialized Output
......
hdl/gn4124core/rtl/spartan3/gn4124_core_pkg.vhd
+ 13
− 7
View file @ 6269b8f0
......@@ -60,9 +60,11 @@ package gn4124_core_pkg is
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_sys_n_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
---------------------------------------------------------
-- P2L Clock Domain
......@@ -133,9 +135,11 @@ package gn4124_core_pkg is
(
---------------------------------------------------------
-- ICLK Clock Domain Inputs
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_sys_n_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_n_i : in std_logic;
l2p_valid_i : in std_logic;
l2p_dframe_i : in std_logic;
......@@ -317,7 +321,8 @@ package gn4124_core_pkg is
l2p_dma_stb_o : out std_logic; -- Read or write strobe
l2p_dma_we_o : out std_logic; -- Write
l2p_dma_ack_i : in std_logic; -- Acknowledge
l2p_dma_stall_i : in std_logic -- for pipelined Wishbone
l2p_dma_stall_i : in std_logic; -- for pipelined Wishbone
p2l_dma_cyc_i : in std_logic -- P2L dma wb cycle (for bus arbitration)
);
end component; -- l2p_dma_master
......@@ -388,6 +393,7 @@ package gn4124_core_pkg is
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- From P2L DMA MASTER
......
hdl/gn4124core/rtl/spartan3/l2p_ser.vhd
+ 93
− 40
View file @ 6269b8f0
......@@ -40,9 +40,11 @@ entity l2p_ser is
(
---------------------------------------------------------
-- Reset and clock
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_sys_n_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Serializer inputs
......@@ -72,10 +74,13 @@ architecture rtl of l2p_ser is
signal ff_rst : std_logic;
-- SDR to DDR signals
signal dframe_d : std_logic;
signal valid_d : std_logic;
signal data_d : std_logic_vector(l2p_data_i'range);
signal l2p_clk_sdr : std_logic;
signal dframe_d : std_logic;
signal valid_d : std_logic;
signal data_d : std_logic_vector(l2p_data_i'range);
signal l2p_dframe_buf : std_logic;
signal l2p_valid_buf : std_logic;
signal l2p_data_buf : std_logic_vector(l2p_data_i'range);
signal l2p_clk_sdr : std_logic;
begin
......@@ -95,13 +100,13 @@ begin
-----------------------------------------------------------------------------
-- Re-allign data tightly for the positive clock edge
-----------------------------------------------------------------------------
process (clk_p_i, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
dframe_d <= '0';
valid_d <= '0';
data_d <= (others => '0');
elsif rising_edge(clk_p_i) then
elsif rising_edge(clk_sys_i) then
dframe_d <= l2p_dframe_i;
valid_d <= l2p_valid_i;
data_d <= l2p_data_i;
......@@ -111,26 +116,69 @@ begin
------------------------------------------------------------------------------
-- Align control signals to the negative clock edge
------------------------------------------------------------------------------
process (clk_n_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
l2p_valid_o <= '0';
l2p_dframe_o <= '0';
elsif rising_edge(clk_n_i) then
l2p_valid_o <= valid_d;
l2p_dframe_o <= dframe_d;
end if;
end process;
-- Spartan3 control signal generation
gen_ctl_s3 : if g_IS_SPARTAN6 = false generate
process (clk_n_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
l2p_valid_o <= '0';
l2p_dframe_o <= '0';
elsif rising_edge(clk_n_i) then
l2p_valid_o <= valid_d;
l2p_dframe_o <= dframe_d;
end if;
end process;
end generate gen_ctl_s3;
-- Spartan6 control signal generation
gen_ctl_s6 : if g_IS_SPARTAN6 = true generate
cmp_ddr_ff_valid : ODDR2
port map
(
Q => l2p_valid_buf,
C0 => clk_p_i,
C1 => clk_n_i,
CE => '1',
D0 => valid_d,
D1 => valid_d,
R => ff_rst,
S => '0'
);
cmp_buf_valid : OBUF
port map (
O => l2p_valid_o,
I => l2p_valid_buf
);
cmp_ddr_ff_dframe : ODDR2
port map
(
Q => l2p_dframe_buf,
C0 => clk_p_i,
C1 => clk_n_i,
CE => '1',
D0 => dframe_d,
D1 => dframe_d,
R => ff_rst,
S => '0'
);
cmp_buf_dframe : OBUF
port map (
O => l2p_dframe_o,
I => l2p_dframe_buf
);
end generate gen_ctl_s6;
------------------------------------------------------------------------------
-- DDR FF instanciation for data
------------------------------------------------------------------------------
-- Spartan3 primitives instanciation
gen_out_ddr_ff : if g_IS_SPARTAN6 = false generate
gen_data_s3 : if g_IS_SPARTAN6 = false generate
-- Data
DDROUT : for i in 0 to 15 generate
U : OFDDRRSE
gen_bits : for i in 0 to 15 generate
cmp_ddr_ff : OFDDRRSE
port map
(
Q => l2p_data_o(i),
......@@ -142,27 +190,32 @@ begin
R => ff_rst,
S => '0'
);
end generate;
end generate gen_out_ddr_ff;
end generate gen_bits;
end generate gen_data_s3;
-- Spartan6 primitives instanciation
gen_out_ddr_ff_s6 : if g_IS_SPARTAN6 = true generate
gen_data_s6 : if g_IS_SPARTAN6 = true generate
-- Data
DDROUT : for i in 0 to 15 generate
U : ODDR2
gen_bits : for i in 0 to 15 generate
cmp_ddr_ff : ODDR2
port map
(
Q => l2p_data_o(i),
C0 => clk_n_i,
C1 => clk_p_i,
Q => l2p_data_buf(i),
C0 => clk_p_i,
C1 => clk_n_i,
CE => '1',
D0 => data_d(i),
D1 => data_d(i+16),
R => ff_rst,
S => '0'
);
end generate;
end generate gen_out_ddr_ff_s6;
cmp_buf : OBUF
port map (
O => l2p_data_o(i),
I => l2p_data_buf(i)
);
end generate gen_bits;
end generate gen_data_s6;
------------------------------------------------------------------------------
-- DDR source synchronous clock generation
......@@ -174,9 +227,9 @@ begin
I => l2p_clk_sdr);
-- Spartan3 primitives instanciation
gen_l2p_clk_ddr_ff : if g_IS_SPARTAN6 = false generate
gen_clk_s3 : if g_IS_SPARTAN6 = false generate
-- L2P clock
L2P_CLK_int : FDDRRSE
cmp_ddr_ff : FDDRRSE
port map(
Q => l2p_clk_sdr,
C0 => clk_n_i,
......@@ -186,22 +239,22 @@ begin
D1 => '0',
R => '0',
S => '0');
end generate gen_l2p_clk_ddr_ff;
end generate gen_clk_s3;
-- Spartan6 primitives instanciation
gen_l2p_clk_ddr_ff_s6 : if g_IS_SPARTAN6 = true generate
gen_clk_s6 : if g_IS_SPARTAN6 = true generate
-- L2P clock
L2P_CLK_int : ODDR2
cmp_ddr_ff : ODDR2
port map(
Q => l2p_clk_sdr,
C0 => clk_n_i,
C1 => clk_p_i,
C0 => clk_sys_i,
C1 => clk_sys_n_i,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate gen_l2p_clk_ddr_ff_s6;
end generate gen_clk_s6;
end rtl;
......
hdl/gn4124core/rtl/spartan3/p2l_des.vhd
+ 77
− 12
View file @ 6269b8f0
......@@ -39,9 +39,11 @@ entity p2l_des is
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_sys_n_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
---------------------------------------------------------
-- P2L clock domain (DDR)
......@@ -76,10 +78,13 @@ architecture rtl of p2l_des is
-- SDR signals
signal p2l_valid_p : std_logic;
signal p2l_valid_n : std_logic;
signal p2l_valid_buf : std_logic;
signal p2l_dframe_p : std_logic;
signal p2l_dframe_n : std_logic;
signal p2l_dframe_buf : std_logic;
signal p2l_data_p : std_logic_vector(p2l_data_i'range);
signal p2l_data_n : std_logic_vector(p2l_data_i'range);
signal p2l_data_buf : std_logic_vector(p2l_data_i'range);
signal p2l_data_sdr_l : std_logic_vector(p2l_data_i'range);
signal p2l_data_sdr : std_logic_vector(p2l_data_i'length*2-1 downto 0);
......@@ -104,7 +109,7 @@ begin
------------------------------------------------------------------------------
-- Spartan3 primitives instanciation
gen_in_ddr_ff : if g_IS_SPARTAN6 = false generate
gen_in_s3 : if g_IS_SPARTAN6 = false generate
-- Data
DDRFF_D : for i in p2l_data_i'range generate
U : IFDDRRSE
......@@ -148,22 +153,82 @@ begin
R => ff_rst,
S => '0'
);
end generate gen_in_ddr_ff;
end generate gen_in_s3;
-- Spartan6 primitives instanciation
gen_in_ddr_ff_s6 : if g_IS_SPARTAN6 = true generate
end generate gen_in_ddr_ff_s6;
gen_in_s6 : if g_IS_SPARTAN6 = true generate
-- Data
gen_data : for i in p2l_data_i'range generate
cmp_buf : IBUF
port map (
O => p2l_data_buf(i),
I => p2l_data_i(i)
);
cmp_ddr_ff : IDDR2
port map
(
Q0 => p2l_data_n(i),
Q1 => p2l_data_p(i),
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_data_buf(i),
R => ff_rst,
S => '0'
);
end generate gen_data;
-- dframe
cmp_buf_dframe : IBUF
port map (
O => p2l_dframe_buf,
I => p2l_dframe_i
);
cmp_ddr_ff_dframe : IDDR2
port map
(
Q0 => p2l_dframe_n,
Q1 => p2l_dframe_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_dframe_buf,
R => ff_rst,
S => '0'
);
-- valid
cmp_buf_valid : IBUF
port map (
O => p2l_valid_buf,
I => p2l_valid_i
);
cmp_ddr_ff_valid : IDDR2
port map
(
Q0 => p2l_valid_n,
Q1 => p2l_valid_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_valid_buf,
R => ff_rst,
S => '0'
);
end generate gen_in_s6;
-----------------------------------------------------------------------------
-- Align positive edge data to negative edge clock
-----------------------------------------------------------------------------
process (clk_n_i, rst_n_i)
process (clk_sys_n_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
p2l_data_sdr_l <= (others => '0');
elsif rising_edge(clk_n_i) then
elsif rising_edge(clk_sys_n_i) then
p2l_data_sdr_l <= p2l_data_p;
end if;
end process;
......@@ -175,13 +240,13 @@ begin
-----------------------------------------------------------------------------
-- Final positive edge clock alignment
-----------------------------------------------------------------------------
process (clk_p_i, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
p2l_valid_o <= '0';
p2l_dframe_o <= '0';
p2l_data_o <= (others => '0');
elsif rising_edge(clk_p_i) then
elsif rising_edge(clk_sys_i) then
p2l_valid_o <= p2l_valid_p;
p2l_dframe_o <= p2l_dframe_p;
p2l_data_o <= p2l_data_sdr;
......
hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+ 1
− 0
View file @ 6269b8f0
......@@ -40,6 +40,7 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity gn4124_core is
generic(
g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
......
hdl/spec/rtl/spec_gn4124_test.vhd
+ 44
− 15
View file @ 6269b8f0
......@@ -100,12 +100,12 @@ architecture rtl of spec_gn4124_test is
component gn4124_core
generic(
--g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
port
(
......@@ -287,8 +287,11 @@ architecture rtl of spec_gn4124_test is
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_k2000 : unsigned(2 downto 0);
signal led_pps : std_logic;
signal leds : std_logic_vector(3 downto 0);
begin
......@@ -313,7 +316,7 @@ begin
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
--g_IS_SPARTAN6 => true,
g_IS_SPARTAN6 => true,
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
......@@ -513,17 +516,43 @@ begin
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
led_en <= '1';
elsif rising_edge(l_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(24);
led_en <= led_cnt(23);
end if;
end process p_led_cnt;
AUX_LEDS_O(0) <= led_en;
AUX_LEDS_O(1) <= not(led_en);
AUX_LEDS_O(2) <= '1';
AUX_LEDS_O(3) <= '0';
led_pps <= led_cnt(23) and not(led_en);
p_led_k2000 : process (l_clk, L_RST_N)
begin
if L_RST_N = '0' then
led_k2000 <= (others => '0');
leds <= "0001";
elsif rising_edge(l_clk) then
if led_pps = '1' then
if led_k2000(2) = '0' then
if leds /= "1000" then
leds <= leds(2 downto 0) & '0';
end if;
else
if leds /= "0001" then
leds <= '0' & leds(3 downto 1);
end if;
end if;
led_k2000 <= led_k2000 + 1;
end if;
end if;
end process p_led_k2000;
AUX_LEDS_O <= not(leds);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
end rtl;
......
hdl/spec/syn/Makefile
+ 4
− 8
View file @ 6269b8f0
......@@ -41,14 +41,10 @@ FILES := ../spec_gn4124_test.ucf \
../../gn4124core/rtl/p2l_decode32.vhd \
../../gn4124core/rtl/p2l_dma_master.vhd \
../../gn4124core/rtl/wbmaster32.vhd \
../../gn4124core/rtl/spartan6/gn4124_core.vhd \
../../gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../gn4124core/rtl/spartan6/l2p_ser.vhd \
../../gn4124core/rtl/spartan6/p2l_des.vhd \
../../gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../gn4124core/rtl/spartan3/gn4124_core.vhd \
../../gn4124core/rtl/spartan3/gn4124_core_pkg.vhd \
../../gn4124core/rtl/spartan3/l2p_ser.vhd \
../../gn4124core/rtl/spartan3/p2l_des.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_moving_average.vhd \
......
hdl/spec/syn/spec_gn4124_test.xise
+ 77
− 82
View file @ 6269b8f0
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