Change wb_write_cnt, wb_read_cnt and wb_ack_cnt width to 32 instead of 7

hdl/gn4124core/rtl/l2p_dma_master.vhd

@@ -126,8 +126,8 @@ architecture behaviour of l2p_dma_master is
   signal data_fifo_full  : std_logic;
 
   -- Wishbone
-  signal wb_read_cnt   : unsigned(6 downto 0);
-  signal wb_ack_cnt    : unsigned(6 downto 0);
+  signal wb_read_cnt   : unsigned(31 downto 0);
+  signal wb_ack_cnt    : unsigned(31 downto 0);
   signal l2p_dma_cyc_t : std_logic;
   signal l2p_dma_stb_t : std_logic;
 
@@ -582,7 +582,7 @@ begin
     end if;
   end process p_wb_read_cnt;
 
--- Wishbone ack counter
+  -- Wishbone ack counter
   p_wb_ack_cnt : process (l2p_dma_clk_i, rst_n_i)
   begin
     if (rst_n_i = c_RST_ACTIVE) then

hdl/gn4124core/rtl/p2l_dma_master.vhd

@@ -163,8 +163,8 @@ architecture behaviour of p2l_dma_master is
   signal to_wb_fifo_byte_swap : std_logic_vector(1 downto 0);
 
   -- wishbone
-  signal wb_write_cnt  : unsigned(6 downto 0);
-  signal wb_ack_cnt    : unsigned(6 downto 0);
+  signal wb_write_cnt  : unsigned(31 downto 0);
+  signal wb_ack_cnt    : unsigned(31 downto 0);
   signal p2l_dma_cyc_t : std_logic;
   signal p2l_dma_stb_t : std_logic;
 
@@ -537,7 +537,7 @@ begin
         p2l_dma_dat_o <= to_wb_fifo_dout(31 downto 0);
       end if;
       -- stb and sel signals management
-      if (to_wb_fifo_valid = '1') then --or (p2l_dma_stall_i = '1' and p2l_dma_stb_t = '1') then
+      if (to_wb_fifo_valid = '1') then  --or (p2l_dma_stall_i = '1' and p2l_dma_stb_t = '1') then
         p2l_dma_stb_t <= '1';
         p2l_dma_sel_o <= (others => '1');
       else