Add lib for top entity. Move syn only files to syn manifest.

hdl/spec/rtl/Manifest.py

-files = ["spec_gn4124_test.vhd",
-         "../spec_gn4124_test.ucf"]
+files = ["spec_gn4124_test.vhd",]
 
 modules = {"local" : ["../../common/rtl",
-                      '../../gn4124/rtl']}
+                      '../../gn4124core/rtl']}

hdl/spec/rtl/spec_gn4124_test.vhd

@@ -26,6 +26,7 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
+use work.gn4124_core_pkg.all;
 
 library UNISIM;
 use UNISIM.vcomponents.all;
@@ -84,6 +85,8 @@ entity spec_gn4124_test is
       );
 end spec_gn4124_test;
 
+
+
 architecture rtl of spec_gn4124_test is
 
   ------------------------------------------------------------------------------
@@ -290,19 +293,6 @@ architecture rtl of spec_gn4124_test is
 
 begin
 
-  ------------------------------------------------------------------------------
-  -- System clock from 25MHz TCXO
-  ------------------------------------------------------------------------------
-  cmp_sysclk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => sys_clk,                    -- Buffer output
-      I  => sys_clk_p,                  -- Diff_p buffer input (connect directly to top-level port)
-      IB => sys_clk_n                   -- Diff_n buffer input (connect directly to top-level port)
-      );
 
   ------------------------------------------------------------------------------
   -- Local clock from gennum LCLK
@@ -452,10 +442,8 @@ begin
       dummy_reg_led_o => dummy_ctrl_reg_led
       );
 
-  LED_RED   <= dummy_ctrl_reg_led(0);
-  LED_GREEN <= dummy_ctrl_reg_led(1);
-  --LED_GREEN <= '1';
-  --LED_RED   <= p2l_pll_locked;
+  led_red_o   <= dummy_ctrl_reg_led(0);
+  led_green_o <= dummy_ctrl_reg_led(1);
 
   ------------------------------------------------------------------------------
   -- DMA wishbone bus connected to a DPRAM

hdl/spec/syn/Manifest.py

@@ -3,8 +3,13 @@ action = "synthesis"
 
 modules = { "local" : "../rtl" }
 
-syn_device = "xc6slx150t"
-syn_grade = "-2"
-syn_package = "fgg676"
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
 syn_top = "spec_gn4124_test"
 syn_project = "spec_gn4124_test.xise"
+
+files = ["../ip_cores/ram_2048x32.ngc",
+         "../ip_cores/fifo_32x512.ngc",
+         "../ip_cores/fifo_64x512.ngc",
+         "../spec_gn4124_test.ucf"]