Add test top for spec. Add Manifest.

hdl/common/rtl/Manifest.py

+files = ["dummy_ctrl_regs.vhd",
+         "dummy_stat_regs.vhd"]

hdl/gn4124core/rtl/Manifest.py

@@ -7,6 +7,5 @@ files = ["dma_controller.vhd",
          "p2l_dma_master.vhd",
          "wbmaster32.vhd"]
 
-modules = { "local" : "spartan6",
-            "git" : "git://ohwr.org/hdl-core-lib/general-cores.git" }
+modules = { "local" : "spartan6" }
 

hdl/gn4124core/rtl/spartan6/Manifest.py

 files = ["gn4124_core.vhd",
-         "gn4124_core_private_pkg.vhd",
+         "gn4124_core_pkg.vhd",
          "l2p_ser.vhd",
          "p2l_des.vhd",
          "serdes_1_to_n_clk_pll_s2_diff.vhd",

hdl/spec/rtl/Manifest.py

+files = ["spec_gn4124_test.vhd",
+         "../spec_gn4124_test.ucf"]
+
+modules = {"local" : ["../../common/rtl",
+                      '../../gn4124/rtl']}

hdl/spec/syn/Manifest.py

+target = "xilinx"
+action = "synthesis"
+
+modules = { "local" : "../rtl" }
+
+syn_device = "xc6slx150t"
+syn_grade = "-2"
+syn_package = "fgg676"
+syn_top = "spec_gn4124_test"
+syn_project = "spec_gn4124_test.xise"