core: Add err, rty and int signals to the wishbone masters interfaces....
core: Add err, rty and int signals to the wishbone masters interfaces. Terminate wb cycle in case of err on csr wb bus.
Note: The wb crossbar asserts err in case of access to un-mapped address.
Therefore to avoid host hang in case of access to un-mapped address,
the wb cycle is terminated (and returns 0xFFFFFFFF in case of read cycle).
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- hdl/gn4124core/rtl/spartan6/gn4124_core.vhd 11 additions, 2 deletionshdl/gn4124core/rtl/spartan6/gn4124_core.vhd
- hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd 11 additions, 2 deletionshdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
- hdl/gn4124core/rtl/wbmaster32.vhd 15 additions, 1 deletionhdl/gn4124core/rtl/wbmaster32.vhd
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