Add top module component declaration in package.

hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd

@@ -52,6 +52,94 @@ package gn4124_core_pkg is
 --! Components declaration
 --==============================================================================
 
+-----------------------------------------------------------------------------
+  component gn4124_core
+    port
+      (
+        ---------------------------------------------------------
+        -- Control and status
+        rst_n_a_i : in  std_logic;                      -- Asynchronous reset from GN4124
+        status_o  : out std_logic_vector(31 downto 0);  -- Core status output
+
+        ---------------------------------------------------------
+        -- P2L Direction
+        --
+        -- Source Sync DDR related signals
+        p2l_clk_p_i  : in  std_logic;                      -- Receiver Source Synchronous Clock+
+        p2l_clk_n_i  : in  std_logic;                      -- Receiver Source Synchronous Clock-
+        p2l_data_i   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+        p2l_dframe_i : in  std_logic;                      -- Receive Frame
+        p2l_valid_i  : in  std_logic;                      -- Receive Data Valid
+        -- P2L Control
+        p2l_rdy_o    : out std_logic;                      -- Rx Buffer Full Flag
+        p_wr_req_i   : in  std_logic_vector(1 downto 0);   -- PCIe Write Request
+        p_wr_rdy_o   : out std_logic_vector(1 downto 0);   -- PCIe Write Ready
+        rx_error_o   : out std_logic;                      -- Receive Error
+        vc_rdy_i     : in  std_logic_vector(1 downto 0);   -- Virtual channel ready
+
+        ---------------------------------------------------------
+        -- L2P Direction
+        --
+        -- Source Sync DDR related signals
+        l2p_clk_p_o  : out std_logic;                      -- Transmitter Source Synchronous Clock+
+        l2p_clk_n_o  : out std_logic;                      -- Transmitter Source Synchronous Clock-
+        l2p_data_o   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+        l2p_dframe_o : out std_logic;                      -- Transmit Data Frame
+        l2p_valid_o  : out std_logic;                      -- Transmit Data Valid
+        -- L2P Control
+        l2p_edb_o    : out std_logic;                      -- Packet termination and discard
+        l2p_rdy_i    : in  std_logic;                      -- Tx Buffer Full Flag
+        l_wr_rdy_i   : in  std_logic_vector(1 downto 0);   -- Local-to-PCIe Write
+        p_rd_d_rdy_i : in  std_logic_vector(1 downto 0);   -- PCIe-to-Local Read Response Data Ready
+        tx_error_i   : in  std_logic;                      -- Transmit Error
+
+        ---------------------------------------------------------
+        -- Interrupt interface
+        dma_irq_o : out std_logic_vector(1 downto 0);  -- Interrupts sources to IRQ manager
+        irq_p_i   : in  std_logic;                     -- Interrupt request pulse from IRQ manager
+        irq_p_o   : out std_logic;                     -- Interrupt request pulse to GN4124 GPIO
+
+        ---------------------------------------------------------
+        -- DMA registers wishbone interface (slave classic)
+        dma_reg_clk_i   : in  std_logic;
+        dma_reg_adr_i   : in  std_logic_vector(31 downto 0);
+        dma_reg_dat_i   : in  std_logic_vector(31 downto 0);
+        dma_reg_sel_i   : in  std_logic_vector(3 downto 0);
+        dma_reg_stb_i   : in  std_logic;
+        dma_reg_we_i    : in  std_logic;
+        dma_reg_cyc_i   : in  std_logic;
+        dma_reg_dat_o   : out std_logic_vector(31 downto 0);
+        dma_reg_ack_o   : out std_logic;
+        dma_reg_stall_o : out std_logic;
+
+        ---------------------------------------------------------
+        -- CSR wishbone interface (master pipelined)
+        csr_clk_i   : in  std_logic;
+        csr_adr_o   : out std_logic_vector(31 downto 0);
+        csr_dat_o   : out std_logic_vector(31 downto 0);
+        csr_sel_o   : out std_logic_vector(3 downto 0);
+        csr_stb_o   : out std_logic;
+        csr_we_o    : out std_logic;
+        csr_cyc_o   : out std_logic;
+        csr_dat_i   : in  std_logic_vector(31 downto 0);
+        csr_ack_i   : in  std_logic;
+        csr_stall_i : in  std_logic;
+
+        ---------------------------------------------------------
+        -- DMA wishbone interface (master pipelined)
+        dma_clk_i   : in  std_logic;
+        dma_adr_o   : out std_logic_vector(31 downto 0);
+        dma_dat_o   : out std_logic_vector(31 downto 0);
+        dma_sel_o   : out std_logic_vector(3 downto 0);
+        dma_stb_o   : out std_logic;
+        dma_we_o    : out std_logic;
+        dma_cyc_o   : out std_logic;
+        dma_dat_i   : in  std_logic_vector(31 downto 0);
+        dma_ack_i   : in  std_logic;
+        dma_stall_i : in  std_logic
+        );
+  end component gn4124_core;
+
 -----------------------------------------------------------------------------
   component p2l_des
     port