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Commit 9a3b4cd8 authored by Matthieu Cattin's avatar Matthieu Cattin
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Replace RAM by generic spram from ohwr general-cores. [TESTED]

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hdl/gn4124core/rtl/Manifest.py
+ 1
− 1
View file @ 9a3b4cd8
......@@ -9,5 +9,5 @@ files = ["dma_controller.vhd",
modules = { "local" : "spartan6",
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git" }
fetchto = "ip_cores"
fetchto = "../ip_cores"
hdl/spec/rtl/Manifest.py
+ 2
− 1
View file @ 9a3b4cd8
files = ["spec_gn4124_test.vhd",]
modules = {"local" : ["../../common/rtl",
'../../gn4124core/rtl']}
"../../gn4124core/rtl",
"../../gn4124core/ip_cores"]}
hdl/spec/rtl/spec_gn4124_test.vhd
+ 20
− 20
View file @ 9a3b4cd8
......@@ -27,6 +27,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -217,15 +218,6 @@ architecture rtl of spec_gn4124_test is
);
end component;
component ram_2048x32
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(10 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(31 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Constants declaration
......@@ -268,7 +260,7 @@ architecture rtl of spec_gn4124_test is
signal dma_we_o : std_logic;
signal dma_ack_i : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall_i : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ram_we : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
......@@ -286,7 +278,7 @@ architecture rtl of spec_gn4124_test is
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-- FOR TESTS
signal debug : std_logic_vector(7 downto 0);
signal debug : std_logic_vector(7 downto 0);
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
......@@ -329,7 +321,7 @@ begin
-- P2L clock PLL locked
p2l_pll_locked => p2l_pll_locked,
-- Debug outputs
debug_o => debug,
debug_o => debug,
---------------------------------------------------------
-- P2L Direction
......@@ -463,15 +455,23 @@ begin
dma_stall_i <= '0';
ram_we(0) <= dma_we_o and dma_cyc_o and dma_stb_o;
ram_we <= dma_we_o and dma_cyc_o and dma_stb_o;
cmp_test_ram : ram_2048x32
port map (
clka => l_clk,
wea => ram_we,
addra => dma_adr_o(10 downto 0),
dina => dma_dat_o,
douta => dma_dat_i
cmp_test_ram : generic_spram
generic map(
g_data_width => 32,
g_size => 2048,
g_with_byte_enable => false,
g_addr_conflict_resolution => "write_first"
)
port map(
rst_n_i => L_RST_N,
clk_i => l_clk,
bwe_i => "0000",
we_i => ram_we,
a_i => dma_adr_o(10 downto 0),
d_i => dma_dat_o,
q_o => dma_dat_i
);
......
hdl/spec/syn/Makefile 0 → 100644
+ 226
− 0
View file @ 9a3b4cd8
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spec_gn4124_test.xise
ISE_CRAP := *.bgn *.html *.tcl *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.unroutes *.ut *.xpi *.xst *_bitgen.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.html *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=pawel
SERVER:=htsynth
R_NAME:=spec_gn4124_test
__test_for_remote_synthesis_variables:
true #dummy
CWD := $(shell pwd)
FILES := ../spec_gn4124_test.ucf \
../rtl/spec_gn4124_test.vhd \
../../common/rtl/dummy_ctrl_regs.vhd \
../../common/rtl/dummy_stat_regs.vhd \
../../gn4124core/rtl/dma_controller.vhd \
../../gn4124core/rtl/dma_controller_wb_slave.vhd \
../../gn4124core/rtl/l2p_arbiter.vhd \
../../gn4124core/rtl/l2p_dma_master.vhd \
../../gn4124core/rtl/p2l_decode32.vhd \
../../gn4124core/rtl/p2l_dma_master.vhd \
../../gn4124core/rtl/wbmaster32.vhd \
../../gn4124core/rtl/spartan6/gn4124_core.vhd \
../../gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../gn4124core/rtl/spartan6/l2p_ser.vhd \
../../gn4124core/rtl/spartan6/p2l_des.vhd \
../../gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../gn4124core/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd \
../../gn4124core/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.wb \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../gn4124core/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
spec_gn4124_test.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && /opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
#target for fetching all modules stored in repositories
fetch: __general-cores_fetch
__general-cores_fetch:
PWD=$(shell pwd); cd ../../gn4124core/ip_cores; if [ -d general-cores ]; then cd general-cores; git pull; else git clone git://ohwr.org/hdl-core-lib/general-cores.git; fi; cd $(PWD)
hdl/spec/syn/Manifest.py
+ 1
− 4
View file @ 9a3b4cd8
......@@ -9,7 +9,4 @@ syn_package = "fgg484"
syn_top = "spec_gn4124_test"
syn_project = "spec_gn4124_test.xise"
files = ["../ip_cores/ram_2048x32.ngc",
"../ip_cores/fifo_32x512.ngc",
"../ip_cores/fifo_64x512.ngc",
"../spec_gn4124_test.ucf"]
files = ["../spec_gn4124_test.ucf"]
hdl/spec/syn/spec_gn4124_test.bin 0 → 100644
+ 0
− 0
View file @ 9a3b4cd8
File added
hdl/spec/syn/spec_gn4124_test.xise 0 → 100644
+ 917
− 0
View file @ 9a3b4cd8
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