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Commit 232d0912 authored by Matthieu Cattin's avatar Matthieu Cattin
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IRQ generator for Gullwing board -> driver tests.

parent 16cb3184
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hdl/gn4124core/rtl/dummy_ctrl_regs.vhd
+ 45
− 11
View file @ 232d0912
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../../GN4124_core/hdl/gn4124core/design/rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_ctrl_regs_wb_slave.wb
-- Created : Wed Nov 10 14:40:05 2010
-- File : ../rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from dummy_ctrl_regs_wb_slave.wb
-- Created : Fri May 13 11:28:38 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_ctrl_regs_wb_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dummy_ctrl_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -26,8 +26,9 @@ entity dummy_ctrl_regs_wb_slave is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 1' in reg: 'DUMMY_1'
-- Ports for PASS_THROUGH field: 'IRQ' in reg: 'DUMMY_1'
dummy_reg_1_o : out std_logic_vector(31 downto 0);
dummy_reg_1_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_reg_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
......@@ -39,7 +40,6 @@ end dummy_ctrl_regs_wb_slave;
architecture syn of dummy_ctrl_regs_wb_slave is
signal dummy_reg_1_int : std_logic_vector(31 downto 0);
signal dummy_reg_2_int : std_logic_vector(31 downto 0);
signal dummy_reg_3_int : std_logic_vector(31 downto 0);
signal dummy_reg_led_int : std_logic_vector(31 downto 0);
......@@ -72,7 +72,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dummy_reg_1_int <= "00000000000000000000000000000000";
dummy_reg_1_wr_o <= '0';
dummy_reg_2_int <= "00000000000000000000000000000000";
dummy_reg_3_int <= "00000000000000000000000000000000";
dummy_reg_led_int <= "00000000000000000000000000000000";
......@@ -82,17 +82,50 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dummy_reg_1_wr_o <= '0';
ack_in_progress <= '0';
else
dummy_reg_1_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
dummy_reg_1_int <= wrdata_reg(31 downto 0);
dummy_reg_1_wr_o <= '1';
else
rddata_reg(31 downto 0) <= dummy_reg_1_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -133,8 +166,9 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Dummy register 1
dummy_reg_1_o <= dummy_reg_1_int;
-- IRQ
-- pass-through field: IRQ in register: DUMMY_1
dummy_reg_1_o <= wrdata_reg(31 downto 0);
-- Dummy register 2
dummy_reg_2_o <= dummy_reg_2_int;
-- Dummy register 3
......
hdl/gn4124core/wb_gen/dummy_ctrl_regs_wb_slave.wb
+ 4
− 2
View file @ 232d0912
......@@ -8,9 +8,11 @@ peripheral {
reg {
name = "DUMMY_1";
prefix = "1";
field {
name = "Dummy register 1";
type = SLV;
name = "IRQ";
description = "Generates an IRQ";
type = PASS_THROUGH;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......
hdl/gullwing/ise_project/gn4124core.xise
+ 3
− 3
View file @ 232d0912
......@@ -89,13 +89,13 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/fifo_32x512.xise" xil_pn:type="FILE_ISE">
<file xil_pn:name="../ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/fifo_64x512.xise" xil_pn:type="FILE_ISE">
<file xil_pn:name="../ip_cores/fifo_64x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ram_2048x32.xise" xil_pn:type="FILE_ISE">
<file xil_pn:name="../ip_cores/ram_2048x32.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
</files>
......
hdl/gullwing/ise_project/gw_wrapper.bin
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− 0
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hdl/gullwing/ise_project/gw_wrapper.bit
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− 0
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hdl/gullwing/ise_project/gw_wrapper.par
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− 97
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hdl/gullwing/ise_project/gw_wrapper.syr
+ 274
− 226
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hdl/gullwing/ise_project/gw_wrapper.twr
+ 1265
− 1230
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hdl/gullwing/rtl/gullwing_wrapper.vhd
+ 1
− 1
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......@@ -533,7 +533,7 @@ begin
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
irq_to_gn4124 <= irq_sources(1) or irq_sources(0) or dummy_ctrl_reg_1(0);
end rtl;
......
hdl/pfc/ip_cores/coregen.cgc
+ 300
− 51
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hdl/pfc/ip_cores/coregen.cgp
+ 19
− 6
View file @ 232d0912
# Date: Fri Jan 7 10:26:57 2011
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx150t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg676
SET speedgrade = -3
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: 6efb58d3
hdl/pfc/ip_cores/fifo_32x512.gise
+ 9
− 24
View file @ 232d0912
......@@ -21,29 +21,14 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8777296749647723518" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8526690310114954833" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1627810207069309888" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_32x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_32x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_32x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_32x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/pfc/ip_cores/fifo_32x512.ngc
+ 1
− 1
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This diff is collapsed.
hdl/pfc/ip_cores/fifo_32x512.xco
+ 3
− 3
View file @ 232d0912
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Nov 18 17:42:21 2010
# Date: Fri Jan 7 10:26:48 2011
#
##############################################################
#
......@@ -27,7 +27,7 @@ SET implementationfiletype = Ngc
SET package = fgg676
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
......@@ -81,4 +81,4 @@ CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: e2dee9cc
# CRC: 67a0ef27
hdl/pfc/ip_cores/fifo_32x512.xise
+ 10
− 4
View file @ 232d0912
......@@ -19,7 +19,13 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_32x512.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="fifo_32x512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
......@@ -42,7 +48,7 @@
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
......@@ -51,8 +57,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_32x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-18T18:42:26" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="EF4034A15BD0CBC1AF0986B45E2627A1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-07T11:26:53" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8B4D5ECA23A72BAA598A3BFFBA924B85" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/pfc/ip_cores/fifo_64x512.gise
+ 9
− 24
View file @ 232d0912
......@@ -21,29 +21,14 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5972887507274424632" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-551874233002477861" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5324370023856713354" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_64x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_64x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_64x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_64x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/pfc/ip_cores/fifo_64x512.ngc
+ 1
− 1
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This diff is collapsed.
hdl/pfc/ip_cores/fifo_64x512.xco
+ 3
− 3
View file @ 232d0912
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Nov 18 17:47:03 2010
# Date: Fri Jan 7 10:35:25 2011
#
##############################################################
#
......@@ -27,7 +27,7 @@ SET implementationfiletype = Ngc
SET package = fgg676
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
......@@ -81,4 +81,4 @@ CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: 9706ce7f
# CRC: 1278c894
hdl/pfc/ip_cores/fifo_64x512.xise
+ 10
− 4
View file @ 232d0912
......@@ -19,7 +19,13 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_64x512.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="fifo_64x512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
......@@ -42,7 +48,7 @@
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
......@@ -51,8 +57,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_64x512" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-18T18:47:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5D46E449EF4B7C39FF549948C9014AAF" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-07T11:35:30" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C54CB5DD4A299865B42DBF323214859D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/pfc/ip_cores/ram_2048x32.gise
+ 9
− 24
View file @ 232d0912
......@@ -21,29 +21,14 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ram_2048x32.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-62837676621408158" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1565671164687018955" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1290103788" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7212324219199821788" xil_pn:start_ts="1290103788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="ram_2048x32.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ram_2048x32.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="ram_2048x32.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ram_2048x32.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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