Commits · 5d3dad56e91a91f898d5912dcb9028003706cbb6 · Projects / Gennum GN4124 core

Dec 06, 2011
- Fix bug in P2L DMA master, was decrementing data counter even if data where... · 5d3dad56
  Matthieu Cattin authored 13 years ago
```
Fix bug in P2L DMA master, was decrementing data counter even if data where not from a completion with ID frame.
```
  5d3dad56
Dec 05, 2011
- Fix bug fixing in DMA controller. Was going to ERROR state without generating an error_irq. · df0c7c58
  Matthieu Cattin authored 13 years ago
  
  df0c7c58
- Add generic async fifo wrapper for Xilinx CoreGen fifos. · f9352132
  Matthieu Cattin authored 13 years ago
  
  f9352132
- Fix bug in DMA controller. Was going to ERROR state without generating an error_irq. · 32ce5ac5
  Matthieu Cattin authored 13 years ago
  
  32ce5ac5
Nov 22, 2011
- Synchronise dma irq pulses to csr_wb clock. · 6b29b77e
  Matthieu Cattin authored 13 years ago
  
  6b29b77e
- Synchronise dma irq pulses to csr_wb clock. · e2212978
  Matthieu Cattin authored 13 years ago
  
  e2212978
Aug 12, 2011
- Add top module component declaration in package. · fc0e1574
  Matthieu Cattin authored 13 years ago
  
  fc0e1574
Aug 09, 2011
- Move general core lib fetch to rtl top Manifest in /spec/rtl · a2c1a9e5
  Matthieu Cattin authored 13 years ago
  
  a2c1a9e5
Aug 03, 2011
- Move simple address decoder to common/rtl/ dir. Regenerated ise project and Makefile. · 462d88f6
  Matthieu Cattin authored 13 years ago
  
  462d88f6
- Move simple address decoder to common/rtl/ dir. · 63711600
  Matthieu Cattin authored 13 years ago
  
  63711600
- Create a status port on top entity of the core. · 44501c64
  Matthieu Cattin authored 13 years ago
  
  44501c64
Aug 02, 2011
- csr wishbone master takes stall into account. Should now be compatible with classic slaves. · f5a7bea2
  Matthieu Cattin authored 13 years ago
  
  f5a7bea2
- csr wishbone address decoder removed from gennum core. · c90f1f36
  Matthieu Cattin authored 13 years ago
  
  c90f1f36
- Test spartan 6 version with serdes at 200MHz. · be664f3d
  Matthieu Cattin authored 13 years ago
  
  be664f3d
Jul 29, 2011
- Test with IODDR2 and BUFIO2. Not working properly -> IO clocking issues. · 81d491bc
  Matthieu Cattin authored 13 years ago
  
  81d491bc
- Test with IODDR2 and BUFIO2. · 6269b8f0
  Matthieu Cattin authored 13 years ago
  
  6269b8f0
Jul 26, 2011
- Bug fix in P2L DMA master, for 1 word length read request last BE was set and it shouldn't · 9d321167
  Matthieu Cattin authored 13 years ago
  
  9d321167
Jul 25, 2011
- Replace RAM by generic spram from ohwr general-cores. [TESTED] · 9a3b4cd8
  Matthieu Cattin authored 13 years ago
  
  9a3b4cd8
Jul 11, 2011
- Replace Xilinx FIFOs by generic ones from ohwr general-cores. · 383a8a24
  Matthieu Cattin authored 13 years ago
  
  383a8a24
Jul 08, 2011
- Add lib for top entity. Move syn only files to syn manifest. · 661d570b
  Matthieu Cattin authored 13 years ago
  
  661d570b
Jul 07, 2011
- Add test top for spec. Add Manifest. · 27fa1403
  Matthieu Cattin authored 13 years ago
  
  27fa1403
- Add Manifest to core dirs. · 58a49dde
  Matthieu Cattin authored 13 years ago
  
  58a49dde
Jun 29, 2011
- modify dir struc and rename _s6 files. · b6c7e149
  Matthieu Cattin authored 13 years ago
  
  b6c7e149
- Cleanup useless files, move files not related to gn4124 core outside of the dir. · ac7056c0
  Matthieu Cattin authored 13 years ago
  
  ac7056c0
- IRQ generator for Gullwing board -> driver tests. · 232d0912
  Matthieu Cattin authored 13 years ago
  
  232d0912
Apr 13, 2011

Bug fix in L2P DMA FSM, was checking l_wr_rdy only before sendind the 1st... · 16cb3184

Matthieu Cattin authored 13 years ago

Bug fix in L2P DMA FSM, was checking l_wr_rdy only before sendind the 1st packet and not for the next packets in case of data split into several packets. Long DMA were causing the GN4124 chip to crash.

16cb3184

Mar 24, 2011
- Change wb_write_cnt, wb_read_cnt and wb_ack_cnt width to 32 instead of 7 · f78f498a
  Matthieu Cattin authored 14 years ago
  
  f78f498a
Feb 24, 2011
- Add fifo cores files to repo. · 2af634b2
  Matthieu Cattin authored 14 years ago
  
  2af634b2
- Add fifo cores files to repo. · 5772b2ba
  Matthieu Cattin authored 14 years ago
  
  5772b2ba
- Add ip_cores dir to repo. · 4867ebbe
  Matthieu Cattin authored 14 years ago
  
  4867ebbe
- Add spec dir to repo. · f82016e3
  Matthieu Cattin authored 14 years ago
  
  f82016e3
Feb 03, 2011
- Remove g_IS_SPARTAN6 generic from core · 4bceb3d8
  Matthieu Cattin authored 14 years ago
  
  4bceb3d8
- Fix bug in packet generator · aaa3f33b
  Matthieu Cattin authored 14 years ago
  
  aaa3f33b
Feb 02, 2011
- Set wishbone bus output signals to 0 (instead of X) when no master is selected · 5bfa00e9
  Matthieu Cattin authored 14 years ago
  
  5bfa00e9
- remove stall from stb generation, every read from fifo is strobed to the wishbone bus · 8dd6b362
  Matthieu Cattin authored 14 years ago
  
  8dd6b362
- Bug fix in FSM, was not properly ending frame when in L2P_WAIT_DATA state · 832bdfee
  Matthieu Cattin authored 14 years ago
```
Remove stall signal from stb generation, -> all read data from fifo are strobed to the wishbone bus.
```
  832bdfee
- Clear stb when waiting for ack in CSR wishbone master · d7a01602
  Matthieu Cattin authored 14 years ago
  
  d7a01602
- Fix bug in log2_ceil function. odd numbers were leading to stack overflow during synthesis · 35669405
  Matthieu Cattin authored 14 years ago
  
  35669405
Jan 31, 2011
- Add wb bus availability chack between the two masters · 530563df
  Matthieu Cattin authored 14 years ago
  
  530563df
- Add FF on l2p_rdy, p_rd_d_rdy, l2p_edb and l_wr_rdy signals · ac375dd9
  Matthieu Cattin authored 14 years ago
  
  ac375dd9