Add fifo cores files to repo.

hdl/spec/ip_cores/coregen.cgp

+# Date: Thu Feb  3 16:41:04 2011
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45t
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = true
+SET workingdirectory = ./tmp/
+
+# CRC: f66dfaab

hdl/spec/ip_cores/fifo_32x512.gise

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_32x512.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_32x512.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_32x512.veo" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_32x512.vho" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>

hdl/spec/ip_cores/fifo_32x512.vhd

+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_32x512.vhd when simulating
+-- the core, fifo_32x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_32x512 IS
+	port (
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_clk: IN std_logic;
+	din: IN std_logic_VECTOR(31 downto 0);
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
+	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
+	dout: OUT std_logic_VECTOR(31 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic;
+	valid: OUT std_logic;
+	prog_full: OUT std_logic);
+END fifo_32x512;
+
+ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
+-- synthesis translate_off
+component wrapped_fifo_32x512
+	port (
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_clk: IN std_logic;
+	din: IN std_logic_VECTOR(31 downto 0);
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
+	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
+	dout: OUT std_logic_VECTOR(31 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic;
+	valid: OUT std_logic;
+	prog_full: OUT std_logic);
+end component;
+
+-- Configuration specification 
+	for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
+		generic map(
+			c_has_int_clk => 0,
+			c_wr_response_latency => 1,
+			c_rd_freq => 1,
+			c_has_srst => 0,
+			c_enable_rst_sync => 1,
+			c_has_rd_data_count => 0,
+			c_din_width => 32,
+			c_has_wr_data_count => 0,
+			c_full_flags_rst_val => 1,
+			c_implementation_type => 2,
+			c_family => "spartan6",
+			c_use_embedded_reg => 0,
+			c_has_wr_rst => 0,
+			c_wr_freq => 1,
+			c_use_dout_rst => 1,
+			c_underflow_low => 0,
+			c_has_meminit_file => 0,
+			c_has_overflow => 0,
+			c_preload_latency => 1,
+			c_dout_width => 32,
+			c_msgon_val => 1,
+			c_rd_depth => 512,
+			c_default_value => "BlankString",
+			c_mif_file_name => "BlankString",
+			c_error_injection_type => 0,
+			c_has_underflow => 0,
+			c_has_rd_rst => 0,
+			c_has_almost_full => 0,
+			c_has_rst => 1,
+			c_data_count_width => 9,
+			c_has_wr_ack => 0,
+			c_use_ecc => 0,
+			c_wr_ack_low => 0,
+			c_common_clock => 0,
+			c_rd_pntr_width => 9,
+			c_use_fwft_data_count => 0,
+			c_has_almost_empty => 0,
+			c_rd_data_count_width => 9,
+			c_enable_rlocs => 0,
+			c_wr_pntr_width => 9,
+			c_overflow_low => 0,
+			c_prog_empty_type => 0,
+			c_optimization_mode => 0,
+			c_wr_data_count_width => 9,
+			c_preload_regs => 0,
+			c_dout_rst_val => "0",
+			c_has_data_count => 0,
+			c_prog_full_thresh_negate_val => 508,
+			c_wr_depth => 512,
+			c_prog_empty_thresh_negate_val => 3,
+			c_prog_empty_thresh_assert_val => 2,
+			c_has_valid => 1,
+			c_init_wr_pntr_val => 0,
+			c_prog_full_thresh_assert_val => 509,
+			c_use_fifo16_flags => 0,
+			c_has_backup => 0,
+			c_valid_low => 0,
+			c_prim_fifo_type => "512x36",
+			c_count_type => 0,
+			c_prog_full_type => 4,
+			c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_32x512
+		port map (
+			rst => rst,
+			wr_clk => wr_clk,
+			rd_clk => rd_clk,
+			din => din,
+			wr_en => wr_en,
+			rd_en => rd_en,
+			prog_full_thresh_assert => prog_full_thresh_assert,
+			prog_full_thresh_negate => prog_full_thresh_negate,
+			dout => dout,
+			full => full,
+			empty => empty,
+			valid => valid,
+			prog_full => prog_full);
+-- synthesis translate_on
+
+END fifo_32x512_a;
+

hdl/spec/ip_cores/fifo_32x512.vho

+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo_32x512
+	port (
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_clk: IN std_logic;
+	din: IN std_logic_VECTOR(31 downto 0);
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
+	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
+	dout: OUT std_logic_VECTOR(31 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic;
+	valid: OUT std_logic;
+	prog_full: OUT std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo_32x512: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_32x512
+		port map (
+			rst => rst,
+			wr_clk => wr_clk,
+			rd_clk => rd_clk,
+			din => din,
+			wr_en => wr_en,
+			rd_en => rd_en,
+			prog_full_thresh_assert => prog_full_thresh_assert,
+			prog_full_thresh_negate => prog_full_thresh_negate,
+			dout => dout,
+			full => full,
+			empty => empty,
+			valid => valid,
+			prog_full => prog_full);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo_32x512.vhd when simulating
+-- the core, fifo_32x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+

hdl/spec/ip_cores/fifo_32x512.xco

+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Thu Feb  3 16:40:52 2011
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45t
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_32x512
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=509
+CSET full_threshold_negate_value=508
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=32
+CSET input_depth=512
+CSET output_data_width=32
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=true
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: adce0ad2

hdl/spec/ip_cores/fifo_64x512.gise

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_64x512.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_64x512.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_64x512.veo" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_64x512.vho" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>

hdl/spec/ip_cores/fifo_64x512.vhd

+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_64x512.vhd when simulating
+-- the core, fifo_64x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_64x512 IS
+	port (
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_clk: IN std_logic;
+	din: IN std_logic_VECTOR(63 downto 0);
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
+	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
+	dout: OUT std_logic_VECTOR(63 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic;
+	valid: OUT std_logic;
+	prog_full: OUT std_logic);
+END fifo_64x512;
+
+ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
+-- synthesis translate_off
+component wrapped_fifo_64x512
+	port (
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_clk: IN std_logic;
+	din: IN std_logic_VECTOR(63 downto 0);
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
+	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
+	dout: OUT std_logic_VECTOR(63 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic;
+	valid: OUT std_logic;
+	prog_full: OUT std_logic);
+end component;
+
+-- Configuration specification 
+	for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
+		generic map(
+			c_has_int_clk => 0,
+			c_wr_response_latency => 1,
+			c_rd_freq => 1,
+			c_has_srst => 0,
+			c_enable_rst_sync => 1,
+			c_has_rd_data_count => 0,
+			c_din_width => 64,
+			c_has_wr_data_count => 0,
+			c_full_flags_rst_val => 1,
+			c_implementation_type => 2,
+			c_family => "spartan6",
+			c_use_embedded_reg => 0,
+			c_has_wr_rst => 0,
+			c_wr_freq => 1,
+			c_use_dout_rst => 1,
+			c_underflow_low => 0,
+			c_has_meminit_file => 0,
+			c_has_overflow => 0,
+			c_preload_latency => 1,
+			c_dout_width => 64,
+			c_msgon_val => 1,
+			c_rd_depth => 512,
+			c_default_value => "BlankString",
+			c_mif_file_name => "BlankString",
+			c_error_injection_type => 0,
+			c_has_underflow => 0,
+			c_has_rd_rst => 0,
+			c_has_almost_full => 0,
+			c_has_rst => 1,
+			c_data_count_width => 9,
+			c_has_wr_ack => 0,
+			c_use_ecc => 0,
+			c_wr_ack_low => 0,
+			c_common_clock => 0,
+			c_rd_pntr_width => 9,
+			c_use_fwft_data_count => 0,
+			c_has_almost_empty => 0,
+			c_rd_data_count_width => 9,
+			c_enable_rlocs => 0,
+			c_wr_pntr_width => 9,
+			c_overflow_low => 0,
+			c_prog_empty_type => 0,
+			c_optimization_mode => 0,
+			c_wr_data_count_width => 9,
+			c_preload_regs => 0,
+			c_dout_rst_val => "0",
+			c_has_data_count => 0,
+			c_prog_full_thresh_negate_val => 508,
+			c_wr_depth => 512,
+			c_prog_empty_thresh_negate_val => 3,
+			c_prog_empty_thresh_assert_val => 2,
+			c_has_valid => 1,
+			c_init_wr_pntr_val => 0,
+			c_prog_full_thresh_assert_val => 509,
+			c_use_fifo16_flags => 0,
+			c_has_backup => 0,
+			c_valid_low => 0,
+			c_prim_fifo_type => "512x72",
+			c_count_type => 0,
+			c_prog_full_type => 4,
+			c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_64x512
+		port map (
+			rst => rst,
+			wr_clk => wr_clk,
+			rd_clk => rd_clk,
+			din => din,
+			wr_en => wr_en,
+			rd_en => rd_en,
+			prog_full_thresh_assert => prog_full_thresh_assert,
+			prog_full_thresh_negate => prog_full_thresh_negate,
+			dout => dout,
+			full => full,
+			empty => empty,
+			valid => valid,
+			prog_full => prog_full);
+-- synthesis translate_on
+
+END fifo_64x512_a;
+

hdl/spec/ip_cores/fifo_64x512.vho

+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo_64x512
+	port (
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_clk: IN std_logic;
+	din: IN std_logic_VECTOR(63 downto 0);
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
+	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
+	dout: OUT std_logic_VECTOR(63 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic;
+	valid: OUT std_logic;
+	prog_full: OUT std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo_64x512: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_64x512
+		port map (
+			rst => rst,
+			wr_clk => wr_clk,
+			rd_clk => rd_clk,
+			din => din,
+			wr_en => wr_en,
+			rd_en => rd_en,
+			prog_full_thresh_assert => prog_full_thresh_assert,
+			prog_full_thresh_negate => prog_full_thresh_negate,
+			dout => dout,
+			full => full,
+			empty => empty,
+			valid => valid,
+			prog_full => prog_full);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo_64x512.vhd when simulating
+-- the core, fifo_64x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+

hdl/spec/ip_cores/fifo_64x512.xco

+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Thu Feb  3 16:45:57 2011
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45t
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_64x512
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=509
+CSET full_threshold_negate_value=508
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=64
+CSET input_depth=512
+CSET output_data_width=64
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=true
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: d8162d61