wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed together

1.1.0 - 2020-07-24
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.0

Added
-----
- hdl: New indirect wishbone master (driven by an address and data register).
- hdl: New memory wrapper for Cheby.
- hdl: Provide a simple vhdl package to generate WB transactions.
- hdl: New wb_xc7_fw_update module.
- bld: Introduce gen_sourceid.py script to generate a package with the source id.

Changed
-------
- bld: gen_buildinfo.py now adds tag and dirty flag.

Fixed
-----
- hdl: regression to gc_sync_ffs introduced by v1.0.4.
- hdl: add dummy generic to generic_dpram in altera.
- hdl: add missing generics to generic_sync_fifo in genram_pkg.
- hdl: avoid f_log2() circular dependencies in gc_extend_pulse.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Previously, the full flag was asserted at g_size-1 when using g_show_ahead.
The new implementation solves this. However, for backward compatibility,
the default is to still use the previous behaviour. Set g_show_ahead_legacy_mode
to false to switch to the new one.

As a generic module to update xc7 firmware.

Used for fpga-dev-id (aka the convention).

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This bugfix has been tested by myself on the latest development version of SPEC-based FMC-ADC, as
well as by M. Lipinski on BTrain test setup.

Closes #23.

The only reason for this is to improve readability and reduce the usage of gc_posedge/gc_negedge, in
case we want to deprecate them in the near future.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

The main reason for doing this is so that all our sync modules are based directly on
gc_sync (instead of using it indirectly through gc_sync_ffs).

Another benefit of this is that the feedback loop of the pulse synchroniser will now be two clock
cycles shorter (one input clock cycle + one output clock cycle), since gc_sync_ffs is using one
more flip-flop compared to gc_sync.

This will also reduce the number of warnings in various synthesis and simulation tools, since
gc_pulse_syncrhonizer is also used by the gc_sync_word modules, as well as the async dual clock
FIFOs.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This was recently introduced by T. Gingold and we both agreed that it is not really adding much
value, as it can be easily replaced by the more versatile combination ofgc_sync + gc_edge_detect.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is necessary in order to properly "emulate" the previous implementation
of the gc_sync_ffs module.

Furthermore, a "new" module has been introduced, the gc_edge_detect, which
combines positive and negative pulse edge detection. gc_negedge and gc_posedge
have been rewritten to use internally the new gc_edge_detect.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is to avoid any confusion caused by g_SYNC_EDGE and g_EDGE
generics used in gc_sync, gc_sync_ffs and gc_sync_edge modules.

Also use capitals for generics as defined by our coding style.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>