Improve comments of gc_sync_word_wr and gc_pulse_synchronizer2

c465b482 · Tristan Gingold · 971c2e77 · c465b482 · c465b482
Commit c465b482 authored May 04, 2020 by Tristan Gingold
Hide whitespace changes
Inline Side-by-side

Showing with 10 additions and 7 deletions

gc_pulse_synchronizer2.vhd modules/common/gc_pulse_synchronizer2.vhd +4 -3

gc_sync_word_wr.vhd modules/common/gc_sync_word_wr.vhd +6 -4

No files found.
--- a/modules/common/gc_pulse_synchronizer2.vhd
+++ b/modules/common/gc_pulse_synchronizer2.vhd
@@ -40,9 +40,10 @@ entity gc_pulse_synchronizer2 is
    -- pulse input ready (clk_in_i domain). When HI, a pulse
    -- coming to d_p_i will be correctly transferred to q_p_o.
    d_ready_o   : out std_logic;
-    -- last pulse input acknowledged. This is an alternative
-    -- status flag to d_ready_o for applications that work better
-    -- with a pulsed ACK instead of a "ready" flag.
+    -- last pulse input acknowledged (clk_in_i domain).
+    -- This is an alternative status flag to d_ready_o for
+    -- applications that work better with a pulsed ACK
+    -- instead of a "ready" flag.
    d_ack_p_o   : out std_logic;
    -- pulse input (clk_in_i domain)
    d_p_i       : in  std_logic;

--- a/modules/common/gc_sync_word_wr.vhd
+++ b/modules/common/gc_sync_word_wr.vhd
@@ -37,7 +37,7 @@ use work.gencores_pkg.all;

 entity gc_sync_word_wr is
  generic (
-    -- automatically write next word when not busy
+    -- Automatically write next word when not busy.
    g_AUTO_WR : boolean  := FALSE;
    g_WIDTH   : positive := 8);
  port (
@@ -47,16 +47,18 @@ entity gc_sync_word_wr is
    --  Output clock and reset
    clk_out_i   : in  std_logic;
    rst_out_n_i : in  std_logic;
-    --  Input data
+    --  Input data (from clk_in_i domain)
    data_i      : in  std_logic_vector (g_WIDTH - 1 downto 0);
-    --  Input control and status
+    --  Input control (from clk_in_i domain)
    --  wr_i is ignored if g_AUTO_WR is set
    wr_i        : in  std_logic := '0';
+    --  Transfer in progress (clk_in_i domain).
    busy_o      : out std_logic;
+    --  Input wr_i has been used (clk_in_i domain).
    ack_o       : out std_logic;
    --  Output data
    data_o      : out std_logic_vector (g_WIDTH - 1 downto 0);
-    --  Output status
+    --  Output status.  Pulse set when the data has been transfered (clk_out_i domain).
    wr_o        : out std_logic);
 end entity;