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498b16c7
Commit
498b16c7
authored
Oct 31, 2017
by
Tomasz Wlostowski
Committed by
Tristan Gingold
Sep 09, 2020
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axi4: add 512-bit data width AXI4-full record, fixed compilation issue in axi->wb bridge
parent
c8c1553e
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2 changed files
with
49 additions
and
1 deletion
+49
-1
axi4_pkg.vhd
modules/axi/axi4_pkg.vhd
+45
-1
xwb_axi4lite_bridge.vhd
modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+4
-0
No files found.
modules/axi/axi4_pkg.vhd
View file @
498b16c7
...
...
@@ -140,7 +140,7 @@ package axi4_pkg is
constant
c_AXI4_RESP_SLVERR
:
std_logic_vector
(
1
downto
0
)
:
=
"10"
;
constant
c_AXI4_RESP_DECERR
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
function
f_axi4_full_to_lite
(
function
f_axi4_full_to_lite
(
f
:
t_axi4_full_master_out_32
)
return
t_axi4_lite_master_out_32
;
...
...
@@ -198,6 +198,50 @@ package axi4_pkg is
);
end
component
;
-- AXI4-Full interface, master output ports, 512 bits
type
t_axi4_full_master_out_512
is
record
ARVALID
:
std_logic
;
AWVALID
:
std_logic
;
BREADY
:
std_logic
;
RREADY
:
std_logic
;
WLAST
:
std_logic
;
WVALID
:
std_logic
;
ARID
:
std_logic_vector
(
11
downto
0
);
AWID
:
std_logic_vector
(
11
downto
0
);
ARBURST
:
std_logic_vector
(
1
downto
0
);
ARLOCK
:
std_logic
;
ARSIZE
:
std_logic_vector
(
2
downto
0
);
AWBURST
:
std_logic_vector
(
1
downto
0
);
AWLOCK
:
std_logic
;
AWSIZE
:
std_logic_vector
(
2
downto
0
);
ARPROT
:
std_logic_vector
(
2
downto
0
);
AWPROT
:
std_logic_vector
(
2
downto
0
);
ARADDR
:
std_logic_vector
(
31
downto
0
);
AWADDR
:
std_logic_vector
(
31
downto
0
);
WDATA
:
std_logic_vector
(
511
downto
0
);
ARCACHE
:
std_logic_vector
(
3
downto
0
);
ARLEN
:
std_logic_vector
(
7
downto
0
);
ARQOS
:
std_logic_vector
(
3
downto
0
);
AWCACHE
:
std_logic_vector
(
3
downto
0
);
AWLEN
:
std_logic_vector
(
7
downto
0
);
AWQOS
:
std_logic_vector
(
3
downto
0
);
WSTRB
:
std_logic_vector
(
31
downto
0
);
end
record
;
-- AXI4-Full interface, master input ports, 512 bits
type
t_axi4_full_master_in_512
is
record
ARREADY
:
std_logic
;
AWREADY
:
std_logic
;
BVALID
:
std_logic
;
RLAST
:
std_logic
;
RVALID
:
std_logic
;
WREADY
:
std_logic
;
BID
:
std_logic_vector
(
11
downto
0
);
RID
:
std_logic_vector
(
11
downto
0
);
BRESP
:
std_logic_vector
(
1
downto
0
);
RRESP
:
std_logic_vector
(
1
downto
0
);
RDATA
:
std_logic_vector
(
511
downto
0
);
end
record
;
end
package
;
package
body
axi4_pkg
is
...
...
modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
View file @
498b16c7
...
...
@@ -179,7 +179,11 @@ begin
state
<=
IDLE
;
end
if
;
<<<<<<<
HEAD
when
RESPONSE_READ
=>
null
;
=======
when
RESPONSE_READ
=>
>>>>>>>
49
d9064
...
axi4
:
add
512
-
bit
data
width
AXI4
-
full
record
,
fixed
compilation
issue
in
axi
->
wb
bridge
if
(
axi4_slave_i
.
RREADY
=
'1'
)
then
axi4_slave_o
.
RVALID
<=
'0'
;
state
<=
IDLE
;
...
...
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