wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator…

wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)

wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator…
wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)
9bd003e5 · Tomasz Wlostowski · Tristan Gingold · 47d69998 · 9bd003e5 · 9bd003e5
Commit 9bd003e5 authored Apr 09, 2020 by Tomasz Wlostowski Committed by Tristan Gingold Sep 09, 2020
Showing with 12 additions and 2 deletions

fine_pulse_gen_kintexultrascale.vhd ...one/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale.vhd +3 -1

xwb_fine_pulse_gen.vhd modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd +9 -1

No files found.
--- a/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale.vhd
+++ b/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale.vhd
@@ -19,6 +19,8 @@ entity fine_pulse_gen_kintexultrascale is
      clk_par_i    : in std_logic;
      clk_serdes_i : in std_logic;

+      rst_serdes_i : in std_logic;
+      
      rst_sys_n_i : in std_logic;
      cont_i      : in std_logic;

@@ -204,7 +206,7 @@ begin
        D(5)      => par_data(2),
        D(6)      => par_data(1),
        D(7)      => par_data(0),
-        RST    => RST,
+        RST    => rst_serdes_i,
        T => '0'
   );


--- a/modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
+++ b/modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
@@ -31,6 +31,8 @@ entity xwb_fine_pulse_gen is

    pulse_o : out std_logic_vector(g_num_channels-1 downto 0);

+    clk_par_o : out std_logic;
+
    slave_i : in  t_wishbone_slave_in;
    slave_o : out t_wishbone_slave_out
    );
@@ -130,6 +132,8 @@ architecture rtl of xwb_fine_pulse_gen is

  signal pll_locked : std_logic;

+  signal rst_serdes : std_logic;
+
 begin

  
@@ -405,7 +409,7 @@ begin
        clk_serdes_i => clk_ser,
        rst_sys_n_i  => rst_sys_n_i,
        trig_p_i     => ch(I).trig_p,
-        cont_i => ch(i).cont,
+        cont_i =>  ch(i).cont,
        coarse_i       => ch(I).mask,
        pol_i        => ch(I).pol,
        pulse_o      => pulse_o(i),
@@ -424,6 +428,7 @@ begin
      port map (
        clk_par_i    => clk_par,
        clk_serdes_i => clk_ser,
+        rst_serdes_i => regs_out.csr_serdes_rst_o,
        rst_sys_n_i  => rst_sys_n_i,
        trig_p_i     => ch(I).trig_p,
        cont_i => ch(i).cont,
@@ -476,7 +481,10 @@ begin
  end generate gen_is_kintex_ultrascale;
  

+  clk_par_o <= clk_par;

+  regs_in.csr_pll_locked_i <= pll_locked;
+  
 end rtl;