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Platform-independent core collection
Commit 85a3419e authored by Tristan Gingold's avatar Tristan Gingold
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Add a testbench for xwb_indirect.

parent a57636ce
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testbench/wishbone/wb_indirect/Manifest.py 0 → 100644
View file @ 85a3419e
action = "simulation"
target = "generic"
sim_top = "tb_wb_indirect"
sim_tool = ""
modules = { "local" : ["../../../", "../../../sim/vhdl"] };
files = ["tb_wb_indirect.vhd"]
testbench/wishbone/wb_indirect/tb_indirect.gtkw 0 → 100644
View file @ 85a3419e
[*]
[*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI
[*] Mon Apr 20 13:42:47 2020
[*]
[dumpfile] "/Users/gingold/work/general-cores/testbench/wishbone/wb_indirect/tb.ghw"
[dumpfile_mtime] "Mon Apr 20 13:26:13 2020"
[dumpfile_size] 6946
[savefile] "/Users/gingold/work/general-cores/testbench/wishbone/wb_indirect/tb_indirect.gtkw"
[timestart] 0
[size] 1603 918
[pos] -1 -1
*-25.749573 20000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_wb_indirect.
[treeopen] top.tb_wb_indirect.inst_xwb_indirect.
[treeopen] top.tb_wb_indirect.inst_xwb_indirect.inst_regs.
[sst_width] 193
[signals_width] 214
[sst_expanded] 1
[sst_vpaned_height] 278
@420
top.tb_wb_indirect.done
@28
top.tb_wb_indirect.clk
top.tb_wb_indirect.rst_n
top.tb_wb_indirect.wb_out.ack
@22
#{top.tb_wb_indirect.wb_out.dat[31:0]} top.tb_wb_indirect.wb_out.dat[31] top.tb_wb_indirect.wb_out.dat[30] top.tb_wb_indirect.wb_out.dat[29] top.tb_wb_indirect.wb_out.dat[28] top.tb_wb_indirect.wb_out.dat[27] top.tb_wb_indirect.wb_out.dat[26] top.tb_wb_indirect.wb_out.dat[25] top.tb_wb_indirect.wb_out.dat[24] top.tb_wb_indirect.wb_out.dat[23] top.tb_wb_indirect.wb_out.dat[22] top.tb_wb_indirect.wb_out.dat[21] top.tb_wb_indirect.wb_out.dat[20] top.tb_wb_indirect.wb_out.dat[19] top.tb_wb_indirect.wb_out.dat[18] top.tb_wb_indirect.wb_out.dat[17] top.tb_wb_indirect.wb_out.dat[16] top.tb_wb_indirect.wb_out.dat[15] top.tb_wb_indirect.wb_out.dat[14] top.tb_wb_indirect.wb_out.dat[13] top.tb_wb_indirect.wb_out.dat[12] top.tb_wb_indirect.wb_out.dat[11] top.tb_wb_indirect.wb_out.dat[10] top.tb_wb_indirect.wb_out.dat[9] top.tb_wb_indirect.wb_out.dat[8] top.tb_wb_indirect.wb_out.dat[7] top.tb_wb_indirect.wb_out.dat[6] top.tb_wb_indirect.wb_out.dat[5] top.tb_wb_indirect.wb_out.dat[4] top.tb_wb_indirect.wb_out.dat[3] top.tb_wb_indirect.wb_out.dat[2] top.tb_wb_indirect.wb_out.dat[1] top.tb_wb_indirect.wb_out.dat[0]
@28
top.tb_wb_indirect.wb_out.err
top.tb_wb_indirect.wb_out.rty
top.tb_wb_indirect.wb_out.stall
@22
#{top.tb_wb_indirect.wb_in.adr[31:0]} top.tb_wb_indirect.wb_in.adr[31] top.tb_wb_indirect.wb_in.adr[30] top.tb_wb_indirect.wb_in.adr[29] top.tb_wb_indirect.wb_in.adr[28] top.tb_wb_indirect.wb_in.adr[27] top.tb_wb_indirect.wb_in.adr[26] top.tb_wb_indirect.wb_in.adr[25] top.tb_wb_indirect.wb_in.adr[24] top.tb_wb_indirect.wb_in.adr[23] top.tb_wb_indirect.wb_in.adr[22] top.tb_wb_indirect.wb_in.adr[21] top.tb_wb_indirect.wb_in.adr[20] top.tb_wb_indirect.wb_in.adr[19] top.tb_wb_indirect.wb_in.adr[18] top.tb_wb_indirect.wb_in.adr[17] top.tb_wb_indirect.wb_in.adr[16] top.tb_wb_indirect.wb_in.adr[15] top.tb_wb_indirect.wb_in.adr[14] top.tb_wb_indirect.wb_in.adr[13] top.tb_wb_indirect.wb_in.adr[12] top.tb_wb_indirect.wb_in.adr[11] top.tb_wb_indirect.wb_in.adr[10] top.tb_wb_indirect.wb_in.adr[9] top.tb_wb_indirect.wb_in.adr[8] top.tb_wb_indirect.wb_in.adr[7] top.tb_wb_indirect.wb_in.adr[6] top.tb_wb_indirect.wb_in.adr[5] top.tb_wb_indirect.wb_in.adr[4] top.tb_wb_indirect.wb_in.adr[3] top.tb_wb_indirect.wb_in.adr[2] top.tb_wb_indirect.wb_in.adr[1] top.tb_wb_indirect.wb_in.adr[0]
@28
top.tb_wb_indirect.wb_in.cyc
@29
top.tb_wb_indirect.wb_in.stb
@22
#{top.tb_wb_indirect.wb_in.dat[31:0]} top.tb_wb_indirect.wb_in.dat[31] top.tb_wb_indirect.wb_in.dat[30] top.tb_wb_indirect.wb_in.dat[29] top.tb_wb_indirect.wb_in.dat[28] top.tb_wb_indirect.wb_in.dat[27] top.tb_wb_indirect.wb_in.dat[26] top.tb_wb_indirect.wb_in.dat[25] top.tb_wb_indirect.wb_in.dat[24] top.tb_wb_indirect.wb_in.dat[23] top.tb_wb_indirect.wb_in.dat[22] top.tb_wb_indirect.wb_in.dat[21] top.tb_wb_indirect.wb_in.dat[20] top.tb_wb_indirect.wb_in.dat[19] top.tb_wb_indirect.wb_in.dat[18] top.tb_wb_indirect.wb_in.dat[17] top.tb_wb_indirect.wb_in.dat[16] top.tb_wb_indirect.wb_in.dat[15] top.tb_wb_indirect.wb_in.dat[14] top.tb_wb_indirect.wb_in.dat[13] top.tb_wb_indirect.wb_in.dat[12] top.tb_wb_indirect.wb_in.dat[11] top.tb_wb_indirect.wb_in.dat[10] top.tb_wb_indirect.wb_in.dat[9] top.tb_wb_indirect.wb_in.dat[8] top.tb_wb_indirect.wb_in.dat[7] top.tb_wb_indirect.wb_in.dat[6] top.tb_wb_indirect.wb_in.dat[5] top.tb_wb_indirect.wb_in.dat[4] top.tb_wb_indirect.wb_in.dat[3] top.tb_wb_indirect.wb_in.dat[2] top.tb_wb_indirect.wb_in.dat[1] top.tb_wb_indirect.wb_in.dat[0]
#{top.tb_wb_indirect.wb_in.sel[3:0]} top.tb_wb_indirect.wb_in.sel[3] top.tb_wb_indirect.wb_in.sel[2] top.tb_wb_indirect.wb_in.sel[1] top.tb_wb_indirect.wb_in.sel[0]
@28
top.tb_wb_indirect.wb_in.we
@200
-xwb_indirect
[pattern_trace] 1
[pattern_trace] 0
testbench/wishbone/wb_indirect/tb_wb_indirect.vhd 0 → 100644
View file @ 85a3419e
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.sim_wishbone.all;
entity tb_wb_indirect is
end tb_wb_indirect;
architecture arch of tb_wb_indirect is
signal rst_n : std_logic;
signal clk : std_logic;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal master_wb_in : t_wishbone_master_in;
signal master_wb_out : t_wishbone_master_out;
signal last_addr : std_logic_vector (31 downto 0);
signal last_data : std_logic_vector (31 downto 0);
-- For end of test.
signal done : boolean := False;
begin
-- Clock.
process
begin
clk <= '0';
wait for 4 ns;
clk <= '1';
wait for 4 ns;
if done then
report "end of test";
wait;
end if;
end process;
rst_n <= '0', '1' after 8 ns;
-- Test process.
process
variable data : std_logic_vector (31 downto 0);
begin
wb_in.cyc <= '0';
wb_in.stb <= '0';
wait until rst_n = '1';
wait until rising_edge (clk);
-- Set the address.
write32_pl (clk, wb_in, wb_out, x"0000_0000", x"0000_2300");
wait until rising_edge (clk);
-- Read data.
read32_pl (clk, wb_in, wb_out, x"0000_0004", data);
assert data = x"0000_2300";
wait until rising_edge (clk);
write32_pl (clk, wb_in, wb_out, x"0000_0004", x"1234_5678");
assert last_addr = x"0000_2304";
assert last_data = x"1234_5678";
read32_pl (clk, wb_in, wb_out, x"0000_0004", data);
assert data = x"0000_2308";
assert last_data = x"1234_5678";
done <= true;
wait;
end process;
inst_xwb_indirect: entity work.xwb_indirect
port map (
rst_n_i => rst_n,
clk_i => clk,
wb_i => wb_in,
wb_o => wb_out,
master_wb_i => master_wb_in,
master_wb_o => master_wb_out);
-- WB slave.
process (clk)
begin
if rising_edge (clk) then
if rst_n = '0' then
master_wb_in <= (rty => '0',
err => '0',
ack => '0',
stall => '0',
dat => (others => 'U'));
else
master_wb_in.ack <= '0';
master_wb_in.stall <= '0';
if (master_wb_out.cyc and master_wb_out.stb) = '1' then
-- Start of transaction.
last_addr <= master_wb_out.adr;
if master_wb_out.we = '1' then
last_data <= master_wb_out.dat;
end if;
master_wb_in.dat <= master_wb_out.adr;
master_wb_in.ack <= '1';
master_wb_in.stall <= '1';
end if;
end if;
end if;
end process;
end arch;
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