Commit 3a61c9d7 authored by Dimitris Lampridis's avatar Dimitris Lampridis

bld: update CHANGELOG

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent e0ecab7f
......@@ -9,21 +9,28 @@ Change Log
- Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
- Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
1.1.0 - TBD
==========
1.1.0 - 2020-07-24
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.0
Added
-----
- [hdl] New indirect wishbone master (driven by an address and data register).
- [hdl] New memory wrapper for Cheby.
- hdl: New indirect wishbone master (driven by an address and data register).
- hdl: New memory wrapper for Cheby.
- hdl: Provide a simple vhdl package to generate WB transactions.
- hdl: New wb_xc7_fw_update module.
- bld: Introduce gen_sourceid.py script to generate a package with the source id.
Changed
-------
- bld: gen_buildinfo.py now adds tag and dirty flag.
Fixed
-----
- [hdl] regression to gc_sync_ffs introduced by v1.0.4.
- [hdl] add dummy generic to generic_dpram in altera.
- [hdl] add missing generics to generic_sync_fifo in genram_pkg.
- [hdl] avoid f_log2() circular dependencies in gc_extend_pulse.
- hdl: regression to gc_sync_ffs introduced by v1.0.4.
- hdl: add dummy generic to generic_dpram in altera.
- hdl: add missing generics to generic_sync_fifo in genram_pkg.
- hdl: avoid f_log2() circular dependencies in gc_extend_pulse.
1.0.4 - 2020-03-26
......
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