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Platform-independent core collection
Commit 295fd91b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tristan Gingold
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xwb_fine_pulse_gen: fix PLL instantiation on Kintex Ultrascale

parent bf538f6e
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Showing with 4 additions and 4 deletions
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
View file @ 295fd91b
......@@ -139,7 +139,7 @@ architecture rtl of fine_pulse_gen_kintexultrascale_shared is
begin
gen_use_Ext_serdes_clock : if not g_use_external_serdes_clock generate
gen_use_Ext_serdes_clock : if g_use_external_serdes_clock generate
-- stub for the moment
clk_ser_o <= clk_ser_ext_i;
clk_par_o <= clk_ref_i;
......@@ -147,7 +147,7 @@ begin
end generate gen_use_Ext_serdes_clock;
gen_use_int_serdes_clock : if g_use_external_serdes_clock generate
gen_use_int_serdes_clock : if not g_use_external_serdes_clock generate
U_MMCM : MMCME3_ADV
generic map (
......
modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
View file @ 295fd91b
......@@ -7,8 +7,8 @@ use work.wishbone_pkg.all;
use work.fpg_wbgen2_pkg.all;
library unisim;
use unisim.VCOMPONENTS.all;
--library unisim;
--use unisim.VCOMPONENTS.all;
entity xwb_fine_pulse_gen is
generic (
......
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