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Platform-independent core collection
Commit a57636ce authored by Tristan Gingold's avatar Tristan Gingold
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sim/vhdl: provide a simple vhdl package to generate WB transactions.

parent 151ea210
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sim/vhdl/Manifest.py 0 → 100644
View file @ a57636ce
files = [ 'sim_wishbone.vhd', 'sim_wishbone16.vhd']
sim/vhdl/sim_wishbone.vhd 0 → 100644
View file @ a57636ce
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sim_wishbone is
-- PL: pipelined versions.
procedure write32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : std_logic_vector (31 downto 0);
data : std_logic_vector (31 downto 0));
procedure read32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : std_logic_vector (31 downto 0);
data : out std_logic_vector (31 downto 0));
procedure write32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : std_logic_vector (31 downto 0));
procedure read32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : out std_logic_vector (31 downto 0));
end sim_wishbone;
package body sim_wishbone is
-- Generate a strobe pulse.
procedure start_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in) is
begin
wb_o.stb <= '1';
loop
wait until rising_edge(clk);
exit when wb_i.stall = '0';
end loop;
wb_o.stb <= '0';
end start_pl;
procedure wait_ack (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in) is
begin
loop
exit when wb_i.ack = '1';
wait until rising_edge(clk);
end loop;
wb_o.cyc <= '0';
wb_o.adr <= (others => 'X');
wb_o.dat <= (others => 'X');
end wait_ack;
procedure write32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : std_logic_vector (31 downto 0);
data : std_logic_vector (31 downto 0)) is
begin
wb_o.adr <= addr;
wb_o.dat <= data;
wb_o.sel <= "1111";
wb_o.we <= '1';
wb_o.cyc <= '1';
start_pl (clk, wb_o, wb_i);
wait_ack (clk, wb_o, wb_i);
end write32_pl;
procedure read32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : std_logic_vector (31 downto 0);
data : out std_logic_vector (31 downto 0)) is
begin
wb_o.adr <= addr;
wb_o.we <= '0';
wb_o.cyc <= '1';
start_pl (clk, wb_o, wb_i);
wait_ack (clk, wb_o, wb_i);
data := wb_i.dat;
end read32_pl;
procedure write32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : std_logic_vector (31 downto 0)) is
begin
write32_pl (clk, wb_o, wb_i, std_logic_vector (to_unsigned(addr, 32)), data);
end write32_pl;
procedure read32_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : out std_logic_vector (31 downto 0)) is
begin
read32_pl (clk, wb_o, wb_i, std_logic_vector (to_unsigned(addr, 32)), data);
end read32_pl;
end sim_wishbone;
sim/vhdl/sim_wishbone16.vhd 0 → 100644
View file @ a57636ce
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sim_wishbone16 is
-- PL: pipelined versions.
procedure write16_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : std_logic_vector (15 downto 0));
procedure read16_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : out std_logic_vector (15 downto 0));
procedure write64be_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : std_logic_vector (63 downto 0));
procedure read64be_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : out std_logic_vector (63 downto 0));
end sim_wishbone16;
use work.sim_wishbone.all;
package body sim_wishbone16 is
procedure write16_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : std_logic_vector (15 downto 0)) is
begin
write32_pl(clk, wb_o, wb_i, addr, x"0000" & data);
end write16_pl;
procedure read16_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : out std_logic_vector (15 downto 0))
is
variable t : std_logic_vector(31 downto 0);
begin
read32_pl(clk, wb_o, wb_i, addr, t);
data := t(15 downto 0);
end read16_pl;
procedure write64be_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : std_logic_vector (63 downto 0)) is
begin
write32_pl(clk, wb_o, wb_i, addr + 0, x"0000" & data (63 downto 48));
write32_pl(clk, wb_o, wb_i, addr + 2, x"0000" & data (47 downto 32));
write32_pl(clk, wb_o, wb_i, addr + 4, x"0000" & data (31 downto 16));
write32_pl(clk, wb_o, wb_i, addr + 6, x"0000" & data (15 downto 00));
end write64be_pl;
procedure read64be_pl (signal clk : std_logic;
signal wb_o: out t_wishbone_master_out;
signal wb_i: in t_wishbone_master_in;
addr : natural;
data : out std_logic_vector (63 downto 0))
is
variable t : std_logic_vector(31 downto 0);
begin
read32_pl(clk, wb_o, wb_i, addr + 0, t);
data (63 downto 48) := t(15 downto 0);
read32_pl(clk, wb_o, wb_i, addr + 2, t);
data (47 downto 32) := t(15 downto 0);
read32_pl(clk, wb_o, wb_i, addr + 4, t);
data (31 downto 16) := t(15 downto 0);
read32_pl(clk, wb_o, wb_i, addr + 6, t);
data (15 downto 00) := t(15 downto 0);
end read64be_pl;
end sim_wishbone16;
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