Commit b694c67c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tristan Gingold

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI…

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed together
parent 2d29017e
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Last update: 2020-05-05
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -129,6 +129,7 @@ begin -- rtl
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
spi_mosi_o <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment