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Platform-independent core collection
Commit 47d69998 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tristan Gingold
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wb_fine_pulse_gen: extend WB registers with separate serdes reset and PLL lock indicator

parent 295fd91b
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Showing with 33 additions and 4 deletions
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.vhd
View file @ 47d69998
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fine_pulse_gen_wb.vhd
-- Author : auto-generated by wbgen2 from fine_pulse_gen_wb.wb
-- Created : Tue Mar 31 17:24:02 2020
-- Created : Wed Apr 8 15:49:26 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_pulse_gen_wb.wb
......@@ -70,6 +70,7 @@ signal fpg_csr_ready_lwb_s0 : std_logic ;
signal fpg_csr_ready_lwb_s1 : std_logic ;
signal fpg_csr_ready_lwb_s2 : std_logic ;
signal fpg_csr_pll_rst_int : std_logic ;
signal fpg_csr_serdes_rst_int : std_logic ;
signal fpg_ocr0_pps_offs_int : std_logic_vector(3 downto 0);
signal fpg_ocr0_fine_int : std_logic_vector(4 downto 0);
signal fpg_ocr0_pol_int : std_logic ;
......@@ -201,6 +202,7 @@ begin
fpg_csr_ready_lwb_delay <= '0';
fpg_csr_ready_lwb_in_progress <= '0';
fpg_csr_pll_rst_int <= '0';
fpg_csr_serdes_rst_int <= '0';
fpg_ocr0_pps_offs_int <= "0000";
fpg_ocr0_fine_int <= "00000";
fpg_ocr0_pol_int <= '0';
......@@ -329,6 +331,7 @@ begin
fpg_csr_force4_int <= wrdata_reg(12);
fpg_csr_force5_int <= wrdata_reg(13);
fpg_csr_pll_rst_int <= wrdata_reg(20);
fpg_csr_serdes_rst_int <= wrdata_reg(21);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -350,8 +353,8 @@ begin
fpg_csr_ready_lwb_in_progress <= '1';
end if;
rddata_reg(20) <= fpg_csr_pll_rst_int;
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(21) <= fpg_csr_serdes_rst_int;
rddata_reg(22) <= regs_i.csr_pll_locked_i;
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
......@@ -850,6 +853,9 @@ end process;
-- PLL Reset
regs_o.csr_pll_rst_o <= fpg_csr_pll_rst_int;
-- Serdes Reset
regs_o.csr_serdes_rst_o <= fpg_csr_serdes_rst_int;
-- PLL Locked
-- WR PPS offset
regs_o.ocr0_pps_offs_o <= fpg_ocr0_pps_offs_int;
-- Fine delay adjust
......
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.wb
View file @ 47d69998
......@@ -116,6 +116,24 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "Serdes Reset";
prefix = "SERDES_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL Locked";
prefix = "PLL_LOCKED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wbgen2_pkg.vhd
View file @ 47d69998
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fine_pulse_gen_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fine_pulse_gen_wb.wb
-- Created : Tue Mar 31 17:24:02 2020
-- Created : Wed Apr 8 15:49:26 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_pulse_gen_wb.wb
......@@ -22,12 +22,14 @@ package fpg_wbgen2_pkg is
type t_fpg_in_registers is record
csr_ready_i : std_logic_vector(5 downto 0);
csr_pll_locked_i : std_logic;
odelay_calib_rdy_i : std_logic;
odelay_calib_taps_i : std_logic_vector(8 downto 0);
end record;
constant c_fpg_in_registers_init_value: t_fpg_in_registers := (
csr_ready_i => (others => '0'),
csr_pll_locked_i => '0',
odelay_calib_rdy_i => '0',
odelay_calib_taps_i => (others => '0')
);
......@@ -50,6 +52,7 @@ package fpg_wbgen2_pkg is
csr_force4_o : std_logic;
csr_force5_o : std_logic;
csr_pll_rst_o : std_logic;
csr_serdes_rst_o : std_logic;
ocr0_pps_offs_o : std_logic_vector(3 downto 0);
ocr0_fine_o : std_logic_vector(4 downto 0);
ocr0_pol_o : std_logic;
......@@ -124,6 +127,7 @@ package fpg_wbgen2_pkg is
csr_force4_o => '0',
csr_force5_o => '0',
csr_pll_rst_o => '0',
csr_serdes_rst_o => '0',
ocr0_pps_offs_o => (others => '0'),
ocr0_fine_o => (others => '0'),
ocr0_pol_o => '0',
......@@ -229,6 +233,7 @@ function "or" (left, right: t_fpg_in_registers) return t_fpg_in_registers is
variable tmp: t_fpg_in_registers;
begin
tmp.csr_ready_i := f_x_to_zero(left.csr_ready_i) or f_x_to_zero(right.csr_ready_i);
tmp.csr_pll_locked_i := f_x_to_zero(left.csr_pll_locked_i) or f_x_to_zero(right.csr_pll_locked_i);
tmp.odelay_calib_rdy_i := f_x_to_zero(left.odelay_calib_rdy_i) or f_x_to_zero(right.odelay_calib_rdy_i);
tmp.odelay_calib_taps_i := f_x_to_zero(left.odelay_calib_taps_i) or f_x_to_zero(right.odelay_calib_taps_i);
return tmp;
......
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