- 29 Jul, 2016 2 commits
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Jan Pospisil authored
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Jan Pospisil authored
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- 28 Jul, 2016 6 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 27 Jul, 2016 2 commits
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Jan Pospisil authored
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Jan Pospisil authored
added glue logic to the SVEC top level entity SvecTopFfpg.vhd (inspired by git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git)
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- 26 Jul, 2016 6 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
used record from ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd for WB signals in whole design
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- 25 Jul, 2016 6 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 06 Jul, 2016 3 commits
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Jan Pospisil authored
added test for external clock pulse generation - not simulated, not tested (ModelSim 10.4d crashing)
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Jan Pospisil authored
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Jan Pospisil authored
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- 05 Jul, 2016 3 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 04 Jul, 2016 5 commits
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Jan Pospisil authored
added trigger latency specification (not implemented yet); renamed some WB registers to better reflect it purpose
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 01 Jul, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
separated registers for delay configuration (for better operability); added basic testbench for "delay configuration"; fixed few bugs around delay configuration; used WBGEN2 generated Verilog constant file for simulation; typos
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Jan Pospisil authored
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- 30 Jun, 2016 3 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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