added basic test for pulse generation

9e19b2b1 · Jan Pospisil · e728dc75 · 9e19b2b1 · 9e19b2b1 · 9e19b2b1
Commit 9e19b2b1 authored Jul 04, 2016 by Jan Pospisil
5 changed files
--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
@@ -68,6 +68,9 @@ begin

    Clk <= Wb_i.Clk;
    Reset <= Wb_i.Rst;
+    
+    -- TODO - simulation workaround until real dual-clock will be implemented
+    SerialStreamClock <= Clk;

    ----------------------------------
    -- Wishbone slave

--- a/hdl/ffpg/sim/testbench/Config.svh
+++ b/hdl/ffpg/sim/testbench/Config.svh
@@ -8,6 +8,9 @@
 `define WB_DATA_WIDTH 32
 `define WB_TAG_WIDTH 0

+// in bits
+`define STREAM_SIZE 65536
+
 `include "ffpg_csr.svh"

 `define GET_WB_WORD_ADDR(WB_BYTE_ADDR) (WB_BYTE_ADDR/(`WB_DATA_WIDTH/8))

--- a/hdl/ffpg/sim/testbench/Testbench.sv
+++ b/hdl/ffpg/sim/testbench/Testbench.sv
@@ -70,8 +70,9 @@ module Testbench;
    initial begin: mainTest
        uvm_config_db #(virtual FFPGInterface)::set(null, "uvm_test_top.*", "dut_vi", LocalInterface);
        uvm_top.finish_on_completion = 0; // not to finish when GUI is used
-        run_test("TestTriggerAdc");
-        //run_test("TestDelayConfiguration");
+        // run_test("TestTriggerAdc");
+        // run_test("TestDelayConfiguration");
+        run_test("TestPulseGeneration");
        $stop();
    end
    

--- a/hdl/ffpg/sim/testbench/TestbenchPackage.sv
+++ b/hdl/ffpg/sim/testbench/TestbenchPackage.sv
@@ -298,6 +298,100 @@ package TestbenchPackage;

    endclass

+    class SeqSetChannel extends uvm_sequence #(td_wb_tx);
+        `uvm_object_utils(SeqSetChannel)
+        
+        rand int Channel;
+        rand int Overflow;
+        rand logic [`WB_DATA_WIDTH-1:0] SetData [0:(`STREAM_SIZE/`WB_DATA_WIDTH)-1];
+        rand logic [`WB_DATA_WIDTH-1:0] ResData [0:(`STREAM_SIZE/`WB_DATA_WIDTH)-1];
+        
+        constraint ChannelConstraint {
+            Channel inside {[1:2]};
+        }
+        
+        constraint OverflowConstraint {
+            Overflow inside {[0:`STREAM_SIZE-1]};
+        }
+        
+        function new (string name = "");
+            super.new(name);
+        endfunction
+
+        task body;
+            td_wb_tx tx;
+            int SetMemBaseAddress = (Channel == 1) ? `GET_WB_WORD_ADDR(`BASE_FFPG_CH1_SET_MEM) : `GET_WB_WORD_ADDR(`BASE_FFPG_CH2_SET_MEM);
+            int ResMemBaseAddress = (Channel == 1) ? `GET_WB_WORD_ADDR(`BASE_FFPG_CH1_RES_MEM) : `GET_WB_WORD_ADDR(`BASE_FFPG_CH2_RES_MEM);
+            int OverflowInWords = (Overflow / `WB_DATA_WIDTH) + 1;
+            
+            // configure overflow
+            tx = td_wb_tx::type_id::create("tx");
+            start_item(tx);
+            assert(tx.randomize());
+            tx.direction_e = WB_B3_DIR_WRITE;
+            tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_OVERFLOW);
+            tx.data = Overflow;
+            finish_item(tx);
+            assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
+            
+            // configure Set and Res data
+            for (int i = 0; i < OverflowInWords; i++) begin
+                // SetData
+                tx = td_wb_tx::type_id::create("tx");
+                start_item(tx);
+                assert(tx.randomize());
+                tx.direction_e = WB_B3_DIR_WRITE;
+                tx.address = SetMemBaseAddress + i;
+                tx.data = SetData[i];
+                finish_item(tx);
+                assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
+                // ResData
+                tx = td_wb_tx::type_id::create("tx");
+                start_item(tx);
+                assert(tx.randomize());
+                tx.direction_e = WB_B3_DIR_WRITE;
+                tx.address = ResMemBaseAddress + i;
+                tx.data = ResData[i];
+                finish_item(tx);
+                assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
+            end
+            
+            // #100; // ??
+
+        endtask
+
+    endclass
+    
+    class SeqStartChannel extends uvm_sequence #(td_wb_tx);
+        `uvm_object_utils(SeqStartChannel)
+        
+        rand int Channel;
+        
+        constraint ChannelConstraint {
+            Channel inside {[1:2]};
+        }
+        
+        function new (string name = "");
+            super.new(name);
+        endfunction
+
+        task body;
+            td_wb_tx tx;
+            int Position = (Channel == 1) ? `FFPG_CONTROL_CH1_MODE_OFFSET : `FFPG_CONTROL_CH2_MODE_OFFSET;
+            
+            tx = td_wb_tx::type_id::create("tx");
+            start_item(tx);
+            assert(tx.randomize());
+            tx.direction_e = WB_B3_DIR_WRITE;
+            tx.address = `GET_WB_WORD_ADDR(`ADDR_FFPG_CONTROL);
+            tx.data = 1 << Position;
+            finish_item(tx);
+            assert(tx.response_e == WB_B3_RESPONSE_ACK_OK);
+            
+        endtask
+
+    endclass
+    
    class TestBase extends uvm_test;
        `uvm_component_utils(TestBase)

@@ -375,4 +469,42 @@ package TestbenchPackage;

    endclass

+    class TestPulseGeneration extends TestBase;
+        `uvm_component_utils(TestPulseGeneration)
+
+        function new(string name, uvm_component parent);
+            super.new(name, parent);
+        endfunction
+
+        function void build_phase(uvm_phase phase);
+            super.build_phase(phase);
+        endfunction
+
+        task run_phase(uvm_phase phase);
+            SeqSetChannel SeqSet;
+            SeqStartChannel SeqStart;
+            
+            phase.raise_objection(this);
+            #100;
+            
+            // configure channel
+            SeqSet = SeqSetChannel::type_id::create("SeqSet");
+            assert(SeqSet.randomize());
+            SeqSet.start(Env_h.WbAgent.seqr);
+
+            #100;
+            
+            // start channel
+            SeqStart = SeqStartChannel::type_id::create("SeqStart");
+            assert(SeqStart.randomize());
+            SeqStart.Channel = SeqSet.Channel;
+            SeqStart.start(Env_h.WbAgent.seqr);
+            
+            #1000;
+            
+            phase.drop_objection(this);
+        endtask
+
+    endclass
+
 endpackage
\ No newline at end of file
--- a/hdl/ffpg/sim/testbench/sim
+++ b/hdl/ffpg/sim/testbench/sim
@@ -5,8 +5,8 @@ add wave -group DUT sim:/Testbench/dut/cFfpgCore/*
 add wave -group WbSlave -r sim:/Testbench/dut/cFfpgCore/cWbSlaveWrapper/*
 add wave -group DacsController sim:/Testbench/dut/cFfpgCore/cDacsController/*
 add wave -group DelayController -r sim:/Testbench/dut/cFfpgCore/cDelayController/*
-add wave -group DelayedPulseGenerator -r sim:/Testbench/dut/cFfpgCore/cDelayedPulseGeneratorCh1/*
-add wave -group DelayedPulseGenerator -r sim:/Testbench/dut/cFfpgCore/cDelayedPulseGeneratorCh2/*
+add wave -group DelayedPulseGeneratorCh1 -r sim:/Testbench/dut/cFfpgCore/cDelayedPulseGeneratorCh1/*
+add wave -group DelayedPulseGeneratorCh2 -r sim:/Testbench/dut/cFfpgCore/cDelayedPulseGeneratorCh2/*

 configure wave -namecolwidth 217
 configure wave -valuecolwidth 100