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FMC DEL 1ns 2cha
Commit ff02b113 authored by Jan Pospisil's avatar Jan Pospisil
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added SVEC synthesis top file and ISE project; fixed code for unsupported VHDL 2008

parent 80a91b70
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Showing with 829 additions and 38 deletions
hdl/ffpg/rtl/Counter.vhd
View file @ ff02b113
......@@ -62,14 +62,14 @@ begin
variable NewValue_b: unsigned(g_Width-1 downto 0) := (others => '0');
begin
if rising_edge(Clk_ik) then
if Reset_ir then
if Reset_ir = '1' then
NewValue_b := (others => '0');
Overflow_o <= '0';
else
Overflow_o <= '0';
if Set_i then
if Set_i = '1' then
NewValue_b := SetValue_ib;
elsif Enable_i then
elsif Enable_i = '1' then
NewValue_b := Value_b + 1;
if NewValue_b = c_StopValue then
Overflow_o <= '1';
......
hdl/ffpg/rtl/DacsController.vhd
View file @ ff02b113
......@@ -54,11 +54,14 @@ architecture syn of DacsController is
constant c_DacFrequencyMax: natural := 20; -- in MHz
constant c_SclkDivsel: std_logic_vector(2 downto 0) := calculateSclkDivsel(g_ClkFrequency, c_DacFrequencyMax);
signal Reset_nr: std_logic;
signal TriggerDacEn, VcxoDacEn: std_logic;
signal TriggerBusy, VcxoBusy: std_logic;
begin
Reset_nr <= not Reset_ir;
TriggerDacEn <= TriggerLoad_i and not TriggerBusy;
VcxoDacEn <= VcxoLoad_i and not VcxoBusy;
......@@ -71,7 +74,7 @@ begin
)
port map (
clk_i => Clk_ik,
rst_n_i => not Reset_ir,
rst_n_i => Reset_nr,
value_i => std_logic_vector(TriggerValue_ib16),
cs_sel_i(0) => TriggerDacEn,
load_i => TriggerDacEn,
......@@ -91,7 +94,7 @@ begin
)
port map (
clk_i => Clk_ik,
rst_n_i => not Reset_ir,
rst_n_i => Reset_nr,
value_i => std_logic_vector(VcxoValue_ib16),
cs_sel_i(0) => VcxoDacEn,
load_i => VcxoDacEn,
......
hdl/ffpg/rtl/DelayController.vhd
View file @ ff02b113
......@@ -38,28 +38,28 @@ begin
pStart: process (clk) is begin
if rising_edge(clk) then
if reset then
if reset = '1' then
activeOutput <= NONE;
d <= (others => '0');
startConfiguration <= '0';
elsif not loadPulse then
elsif loadPulse = '0' then
startConfiguration <= '0';
if ch1_set_load then
if ch1_set_load = '1' then
activeOutput <= CH1_SET;
d <= ch1_set_value;
startConfiguration <= '1';
end if;
if ch1_reset_load then
if ch1_reset_load = '1' then
activeOutput <= CH1_RESET;
d <= ch1_reset_value;
startConfiguration <= '1';
end if;
if ch2_set_load then
if ch2_set_load = '1' then
activeOutput <= CH2_SET;
d <= ch2_set_value;
startConfiguration <= '1';
end if;
if ch2_reset_load then
if ch2_reset_load = '1' then
activeOutput <= CH2_RESET;
d <= ch2_reset_value;
startConfiguration <= '1';
......
hdl/ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
View file @ ff02b113
......@@ -39,11 +39,11 @@ begin
pFsmTransitions: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if Reset_ir then
if Reset_ir = '1' then
State <= c_ResetState;
else
State <= State;
if ModeLoad_i then
if ModeLoad_i = '1' then
-- global paths
if Mode_i = e_ModeStop then
-- stop command
......@@ -56,11 +56,11 @@ begin
-- separate states
case State is
when s_WaitForTrigger =>
if Trigger_i then
if Trigger_i = '1' then
State <= s_Generating;
end if;
when s_Generating =>
if StreamReset_i then
if StreamReset_i = '1' then
State <= s_Outputting;
end if;
when s_Outputting =>
......@@ -68,7 +68,7 @@ begin
State <= s_WaitForEnd;
end if;
when s_WaitForEnd =>
if StreamReset_i then
if StreamReset_i = '1' then
State <= s_Stop;
end if;
when others =>
......
hdl/ffpg/rtl/DelayedPulseGenerator/RfClkDomain.vhd
View file @ ff02b113
......@@ -140,11 +140,11 @@ begin
);
SetStream_o <=
SetStream when OutputEnable else
SetStream when OutputEnable = '1' else
'0';
ResetStream_o <=
ResetStream when OutputEnable else
ResetStream when OutputEnable = '1' else
'0';
end architecture;
\ No newline at end of file
hdl/ffpg/rtl/FfpgCore.vhd
View file @ ff02b113
......@@ -87,6 +87,8 @@ architecture syn of FfpgCore is
3 => f_sdb_embed_repo_url(c_SdbRepoUrl)
);
signal Reset_nr: std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal CnxMasterOut: t_wishbone_master_out_array(c_NumWbSlaves-1 downto 0);
signal CnxMasterIn: t_wishbone_master_in_array(c_NumWbSlaves-1 downto 0);
......@@ -100,6 +102,8 @@ architecture syn of FfpgCore is
begin
Reset_nr <= not Reset_ir;
----------------------------------
-- WB crossbar
----------------------------------
......@@ -115,7 +119,7 @@ begin
)
port map (
clk_sys_i => Clk_ik,
rst_n_i => not Reset_ir,
rst_n_i => Reset_nr,
slave_i => CnxSlaveIn,
slave_o => CnxSlaveOut,
master_i => CnxMasterIn,
......@@ -173,7 +177,7 @@ begin
)
port map (
clk_sys_i => Clk_ik,
rst_n_i => not Reset_ir,
rst_n_i => Reset_nr,
slave_i => CnxMasterOut(c_SlaveSpiId),
slave_o => CnxMasterIn(c_SlaveSpiId),
desc_o => open,
......
hdl/ffpg/rtl/FfpgPkg.vhd
View file @ ff02b113
......@@ -55,7 +55,7 @@ package body FfpgPkg is
when e_ModeStop => Result := "00";
when e_ModeContinuous => Result := "01";
when e_ModeSingle => Result := "10";
when others => Result := "00";
--when others => Result := "00";
end case;
return Result;
end function;
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ ff02b113
......@@ -198,6 +198,7 @@ begin
----------------------------------
Clk2Sel_o <= WbRegsOutput.control_clock_selection_o(0);
WbRegsInput.control_clock_selection_i <= WbRegsOutput.control_clock_selection_o;
----------------------------------
-- to be used
......
hdl/ffpg/rtl/RegSyncer.vhd
View file @ ff02b113
......@@ -64,9 +64,9 @@ begin
pRs: process (ClkIn_ik) is begin
if rising_edge(ClkIn_ik) then
if ResetNewDataPulse then
if ResetNewDataPulse = '1' then
NewData <= '0';
elsif Load_i then
elsif Load_i = '1' then
-- This load can be missed for processing if arrive to early, i.e. before
-- ResetNewDataPulse corresponding to the previous Load_i.
NewData <= '1';
......
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ ff02b113
......@@ -32,6 +32,8 @@ end entity;
architecture syn of WbSlaveWrapper is
signal Reset_nr: std_logic;
signal WbRegsInput: t_ffpg_in_registers;
signal WbRegsOutput: t_ffpg_out_registers;
......@@ -64,9 +66,11 @@ architecture syn of WbSlaveWrapper is
begin
Reset_nr <= not Reset_ir;
cWbSlave: entity work.ffpg_csr(syn)
port map (
rst_n_i => not Reset_ir,
rst_n_i => Reset_nr,
clk_sys_i => Clk_ik,
wb_adr_i => Wb_i.adr(13 downto 0),
wb_dat_i => Wb_i.dat,
......@@ -113,58 +117,59 @@ begin
overflow_load <= '0';
trigger_latency_load <= '0';
if WbRegsOutput.control_clock_selection_load_o then
if WbRegsOutput.control_clock_selection_load_o = '1' then
control_clock_selection <= WbRegsOutput.control_clock_selection_o;
control_clock_selection_load <= '1';
end if;
if WbRegsOutput.control_ch1_mode_load_o then
if WbRegsOutput.control_ch1_mode_load_o = '1' then
control_ch1_mode <= WbRegsOutput.control_ch1_mode_o;
control_ch1_mode_load <= '1';
end if;
if WbRegsOutput.control_ch2_mode_load_o then
if WbRegsOutput.control_ch2_mode_load_o = '1' then
control_ch2_mode <= WbRegsOutput.control_ch2_mode_o;
control_ch2_mode_load <= '1';
end if;
if WbRegsOutput.vcxo_voltage_load_o then
if WbRegsOutput.vcxo_voltage_load_o = '1' then
vcxo_voltage <= WbRegsOutput.vcxo_voltage_o;
vcxo_voltage_load <= '1';
end if;
if WbRegsOutput.clock_divider_hi_load_o then
if WbRegsOutput.clock_divider_hi_load_o = '1' then
clock_divider_hi <= WbRegsOutput.clock_divider_hi_o;
clock_divider_hi_load <= '1';
end if;
if WbRegsOutput.ch1_delay_set_load_o then
if WbRegsOutput.ch1_delay_set_load_o = '1' then
ch1_delay_set <= WbRegsOutput.ch1_delay_set_o;
ch1_delay_set_load <= '1';
end if;
if WbRegsOutput.ch1_delay_reset_load_o then
if WbRegsOutput.ch1_delay_reset_load_o = '1' then
ch1_delay_reset <= WbRegsOutput.ch1_delay_reset_o;
ch1_delay_reset_load <= '1';
end if;
if WbRegsOutput.ch2_delay_set_load_o then
if WbRegsOutput.ch2_delay_set_load_o = '1' then
ch2_delay_set <= WbRegsOutput.ch2_delay_set_o;
ch2_delay_set_load <= '1';
end if;
if WbRegsOutput.ch2_delay_reset_load_o then
if WbRegsOutput.ch2_delay_reset_load_o = '1' then
ch2_delay_reset <= WbRegsOutput.ch2_delay_reset_o;
ch2_delay_reset_load <= '1';
end if;
if WbRegsOutput.trigger_threshold_load_o then
if WbRegsOutput.trigger_threshold_load_o = '1' then
trigger_threshold <= WbRegsOutput.trigger_threshold_o;
trigger_threshold_load <= '1';
end if;
if WbRegsOutput.overflow_load_o then
if WbRegsOutput.overflow_load_o = '1' then
overflow <= WbRegsOutput.overflow_o;
overflow_load <= '1';
end if;
if WbRegsOutput.trigger_latency_load_o then
if WbRegsOutput.trigger_latency_load_o = '1' then
trigger_latency <= WbRegsOutput.trigger_latency_o;
trigger_latency_load <= '1';
end if;
end if;
end process;
pInputRegisters: process (all) is begin
pInputRegisters: process (WbRegs_i, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, trigger_latency) is begin
-- #!@& ISE doesn't know VHDL 2008
-- by default, all values are passed
WbRegsInput <= WbRegs_i;
-- LOAD_EXT inputs are overwritten by local registers
......@@ -182,7 +187,8 @@ begin
WbRegsInput.trigger_latency_i <= trigger_latency;
end process;
pOutputRegisters: process (all) is begin
pOutputRegisters: process (WbRegsOutput, control_clock_selection, control_ch1_mode, control_ch2_mode, vcxo_voltage, clock_divider_hi, ch1_delay_set, ch1_delay_reset, ch2_delay_set, ch2_delay_reset, trigger_threshold, overflow, control_clock_selection_load, control_ch1_mode_load, control_ch2_mode_load, vcxo_voltage_load, clock_divider_hi_load, ch1_delay_set_load, ch1_delay_reset_load, ch2_delay_set_load, ch2_delay_reset_load, trigger_threshold_load, overflow_load, trigger_latency_load) is begin
-- #!@& ISE doesn't know VHDL 2008
-- by default, all values are passed
WbRegs_o <= WbRegsOutput;
-- LOAD_EXT inputs are overwritten by local registers
......
hdl/svec/rtl/SvecTopFfpg.vhd 0 → 100644
View file @ ff02b113
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hdl/svec/syn/SvecFfpg.xise 0 → 100644
View file @ ff02b113
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