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FMC DEL 1ns 2cha
Commit 35d5e2a7 authored by Jan Pospisil's avatar Jan Pospisil
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changed some SLV to UNSIGNED

parent 63c67489
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Showing with 53 additions and 53 deletions
hdl/ffpg/rtl/DacsController.vhd
View file @ 35d5e2a7
......@@ -11,9 +11,9 @@ entity DacsController is
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
TriggerValue_ib16: in std_logic_vector(15 downto 0);
TriggerValue_ib16: in unsigned(15 downto 0);
TriggerLoad_i: in std_logic;
VcxoValue_ib16: in std_logic_vector(15 downto 0);
VcxoValue_ib16: in unsigned(15 downto 0);
VcxoLoad_i: in std_logic;
TriggerDac_o: out t_Ad5600Interface;
VcxoDac_o: out t_Ad5600Interface;
......@@ -72,7 +72,7 @@ begin
port map (
clk_i => Clk_ik,
rst_n_i => not Reset_ir,
value_i => TriggerValue_ib16,
value_i => std_logic_vector(TriggerValue_ib16),
cs_sel_i(0) => TriggerDacEn,
load_i => TriggerDacEn,
sclk_divsel_i => c_SclkDivsel,
......@@ -92,7 +92,7 @@ begin
port map (
clk_i => Clk_ik,
rst_n_i => not Reset_ir,
value_i => VcxoValue_ib16,
value_i => std_logic_vector(VcxoValue_ib16),
cs_sel_i(0) => VcxoDacEn,
load_i => VcxoDacEn,
sclk_divsel_i => c_SclkDivsel,
......
hdl/ffpg/rtl/DelayController.vhd
View file @ 35d5e2a7
......@@ -9,15 +9,15 @@ entity DelayController is
port (
clk: in std_logic;
reset: in std_logic;
ch1_set_value: in std_logic_vector(9 downto 0);
ch1_set_value: in unsigned(9 downto 0);
ch1_set_load: in std_logic;
ch1_reset_value: in std_logic_vector(9 downto 0);
ch1_reset_value: in unsigned(9 downto 0);
ch1_reset_load: in std_logic;
ch2_set_value: in std_logic_vector(9 downto 0);
ch2_set_value: in unsigned(9 downto 0);
ch2_set_load: in std_logic;
ch2_reset_value: in std_logic_vector(9 downto 0);
ch2_reset_value: in unsigned(9 downto 0);
ch2_reset_load: in std_logic;
d: out std_logic_vector(9 downto 0);
d: out unsigned(9 downto 0);
ch1_le_set: out std_logic;
ch1_le_res: out std_logic;
ch2_le_set: out std_logic;
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ 35d5e2a7
......@@ -29,7 +29,7 @@ entity FfpgCore is
ch1_out_en: out std_logic;
ch2_out_en: out std_logic;
-- delay configuration
d: out std_logic_vector(9 downto 0);
d: out unsigned(9 downto 0);
ch_1_le_set: out std_logic;
ch_1_le_res: out std_logic;
ch_2_le_set: out std_logic;
......@@ -47,17 +47,17 @@ architecture syn of FfpgCore is
signal SerialStreamClock: std_logic;
signal Ch1SetMemAddress_b11: std_logic_vector(10 downto 0);
signal Ch1SetMemData_b32: std_logic_vector(31 downto 0);
signal Ch1SetMemAddress_b11: unsigned(10 downto 0);
signal Ch1SetMemData_b32: unsigned(31 downto 0);
signal Ch1SetMemReadStrobe: std_logic;
signal Ch1ResMemAddress_b11: std_logic_vector(10 downto 0);
signal Ch1ResMemData_b32: std_logic_vector(31 downto 0);
signal Ch1ResMemAddress_b11: unsigned(10 downto 0);
signal Ch1ResMemData_b32: unsigned(31 downto 0);
signal Ch1ResMemReadStrobe: std_logic;
signal Ch2SetMemAddress_b11: std_logic_vector(10 downto 0);
signal Ch2SetMemData_b32: std_logic_vector(31 downto 0);
signal Ch2SetMemAddress_b11: unsigned(10 downto 0);
signal Ch2SetMemData_b32: unsigned(31 downto 0);
signal Ch2SetMemReadStrobe: std_logic;
signal Ch2ResMemAddress_b11: std_logic_vector(10 downto 0);
signal Ch2ResMemData_b32: std_logic_vector(31 downto 0);
signal Ch2ResMemAddress_b11: unsigned(10 downto 0);
signal Ch2ResMemData_b32: unsigned(31 downto 0);
signal Ch2ResMemReadStrobe: std_logic;
signal WbRegsInput: t_ffpg_in_registers;
......
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ 35d5e2a7
......@@ -10,17 +10,17 @@ entity WbSlaveWrapper is
Wb_i: in t_WbInterfaceMosi;
Wb_o: out t_WbInterfaceMiso;
SerialStreamClock_i: in std_logic;
Ch1SetMemAddress_ib11: in std_logic_vector(10 downto 0);
Ch1SetMemData_ob32: out std_logic_vector(31 downto 0);
Ch1SetMemAddress_ib11: in unsigned(10 downto 0);
Ch1SetMemData_ob32: out unsigned(31 downto 0);
Ch1SetMemReadStrobe_i: in std_logic;
Ch1ResMemAddress_ib11: in std_logic_vector(10 downto 0);
Ch1ResMemData_ob32: out std_logic_vector(31 downto 0);
Ch1ResMemAddress_ib11: in unsigned(10 downto 0);
Ch1ResMemData_ob32: out unsigned(31 downto 0);
Ch1ResMemReadStrobe_i: in std_logic;
Ch2SetMemAddress_ib11: in std_logic_vector(10 downto 0);
Ch2SetMemData_ob32: out std_logic_vector(31 downto 0);
Ch2SetMemAddress_ib11: in unsigned(10 downto 0);
Ch2SetMemData_ob32: out unsigned(31 downto 0);
Ch2SetMemReadStrobe_i: in std_logic;
Ch2ResMemAddress_ib11: in std_logic_vector(10 downto 0);
Ch2ResMemData_ob32: out std_logic_vector(31 downto 0);
Ch2ResMemAddress_ib11: in unsigned(10 downto 0);
Ch2ResMemData_ob32: out unsigned(31 downto 0);
Ch2ResMemReadStrobe_i: in std_logic;
WbRegs_i: in t_ffpg_in_registers;
WbRegs_o: out t_ffpg_out_registers
......@@ -36,14 +36,14 @@ architecture syn of WbSlaveWrapper is
signal control_clock_selection: std_logic_vector(1 downto 0);
signal control_ch1_mode: std_logic_vector(1 downto 0);
signal control_ch2_mode: std_logic_vector(1 downto 0);
signal vcxo_register: std_logic_vector(15 downto 0);
signal clock_divider_hi: std_logic_vector(3 downto 0);
signal ch1_delay_set: std_logic_vector(9 downto 0);
signal ch1_delay_reset: std_logic_vector(9 downto 0);
signal ch2_delay_set: std_logic_vector(9 downto 0);
signal ch2_delay_reset: std_logic_vector(9 downto 0);
signal trigger_register: std_logic_vector(15 downto 0);
signal overflow: std_logic_vector(15 downto 0);
signal vcxo_register: unsigned(15 downto 0);
signal clock_divider_hi: unsigned(3 downto 0);
signal ch1_delay_set: unsigned(9 downto 0);
signal ch1_delay_reset: unsigned(9 downto 0);
signal ch2_delay_set: unsigned(9 downto 0);
signal ch2_delay_reset: unsigned(9 downto 0);
signal trigger_register: unsigned(15 downto 0);
signal overflow: unsigned(15 downto 0);
-- delayed load signals for LOAD_EXT fields
signal control_clock_selection_load: std_logic;
signal control_ch1_mode_load: std_logic;
......@@ -73,17 +73,17 @@ begin
wb_ack_o => Wb_o.Ack,
wb_stall_o => Wb_o.Stall,
serial_stream_clk_ik => SerialStreamClock_i,
ffpg_ch1_set_mem_addr_i => Ch1SetMemAddress_ib11,
ffpg_ch1_set_mem_data_o => Ch1SetMemData_ob32,
ffpg_ch1_set_mem_addr_i => std_logic_vector(Ch1SetMemAddress_ib11),
unsigned(ffpg_ch1_set_mem_data_o) => Ch1SetMemData_ob32,
ffpg_ch1_set_mem_rd_i => Ch1SetMemReadStrobe_i,
ffpg_ch1_res_mem_addr_i => Ch1ResMemAddress_ib11,
ffpg_ch1_res_mem_data_o => Ch1ResMemData_ob32,
ffpg_ch1_res_mem_addr_i => std_logic_vector(Ch1ResMemAddress_ib11),
unsigned(ffpg_ch1_res_mem_data_o) => Ch1ResMemData_ob32,
ffpg_ch1_res_mem_rd_i => Ch1ResMemReadStrobe_i,
ffpg_ch2_set_mem_addr_i => Ch2SetMemAddress_ib11,
ffpg_ch2_set_mem_data_o => Ch2SetMemData_ob32,
ffpg_ch2_set_mem_addr_i => std_logic_vector(Ch2SetMemAddress_ib11),
unsigned(ffpg_ch2_set_mem_data_o) => Ch2SetMemData_ob32,
ffpg_ch2_set_mem_rd_i => Ch2SetMemReadStrobe_i,
ffpg_ch2_res_mem_addr_i => Ch2ResMemAddress_ib11,
ffpg_ch2_res_mem_data_o => Ch2ResMemData_ob32,
ffpg_ch2_res_mem_addr_i => std_logic_vector(Ch2ResMemAddress_ib11),
unsigned(ffpg_ch2_res_mem_data_o) => Ch2ResMemData_ob32,
ffpg_ch2_res_mem_rd_i => Ch2ResMemReadStrobe_i,
regs_i => WbRegsInput,
regs_o => WbRegsOutput
......
hdl/ffpg/sim/testbench/FfpgCoreWrapper.vhd
View file @ 35d5e2a7
......@@ -29,7 +29,7 @@ entity FfpgCoreWrapper is
VcxoDacSerialData: out std_logic;
ch1_out_en: out std_logic;
ch2_out_en: out std_logic;
d: out std_logic_vector(9 downto 0);
d: out unsigned(9 downto 0);
ch_1_le_set: out std_logic;
ch_1_le_res: out std_logic;
ch_2_le_set: out std_logic;
......
hdl/ffpg/wb_gen/ffpg_csr.wb
View file @ 35d5e2a7
......@@ -153,7 +153,7 @@ peripheral {
field {
name = "VCXO voltage register value";
type = SLV;
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -170,7 +170,7 @@ peripheral {
name = "Clock divider LO value";
description = "Number of clock cycles output stays low.";
prefix = "lo";
type = SLV;
type = UNSIGNED;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -180,7 +180,7 @@ peripheral {
name = "Clock divider HI value";
description = "Number of clock cycles output stays high.";
prefix = "hi";
type = SLV;
type = UNSIGNED;
size = 4;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -195,7 +195,7 @@ peripheral {
field {
name = "CH1 SET delay";
type = SLV;
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -211,7 +211,7 @@ peripheral {
field {
name = "CH1 RES delay";
type = SLV;
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -226,7 +226,7 @@ peripheral {
field {
name = "CH2 SET delay";
type = SLV;
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -242,7 +242,7 @@ peripheral {
field {
name = "CH2 RES delay";
type = SLV;
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -257,7 +257,7 @@ peripheral {
field {
name = "Trigger threshold voltage register value";
type = SLV;
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -272,7 +272,7 @@ peripheral {
field {
name = "Overflow value";
type = SLV;
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
......@@ -287,7 +287,7 @@ peripheral {
field {
name = "Clock frequency value";
type = SLV;
type = UNSIGNED;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......
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