Skip to content

F
FMC DEL 1ns 2cha
Commit 1f9e5784 authored by Jan Pospisil's avatar Jan Pospisil
Browse files
Options

reporting improved

parent ab21bab9
Hide whitespace changes
Inline Side-by-side
Showing with 41 additions and 10 deletions
.gitignore
View file @ 1f9e5784
......@@ -10,3 +10,4 @@
/hdl/ffpg/sim/testbench/uvm.log
/hdl/ffpg/sim/testbench/vsim.wlf
/hdl/ffpg/sim/testbench/wlf*
/hdl/ffpg/sim/testbench/*.vstf
hdl/ffpg/sim/testbench/FfpgFmcPackage.sv
View file @ 1f9e5784
......@@ -31,10 +31,11 @@ package FfpgFmcPackage;
constraint ClockPeriodConstrain {
ClockPeriod inside {[2:200]};
ClockPeriod % 2 == 0;
}
constraint TriggerPeriodicityConstrain {
TriggerPeriodicity inside {[10:50]};
TriggerPeriodicity inside {[10:1000]};
}
constraint TriggerPhaseConstrain {
......@@ -42,7 +43,7 @@ package FfpgFmcPackage;
}
constraint CyclesConstraint {
Cycles inside {[20:100]};
Cycles inside {[20:70]};
}
function new (string name = "");
......@@ -51,7 +52,7 @@ package FfpgFmcPackage;
function string convert2string;
return $sformatf(
"Clock period: %d ns (%f MHz), Trigger periodicity: %d cycles, Trigger phase: %d ns",
"Clock period: %0d ns (%.3f MHz), Trigger periodicity: %0d cycles, Trigger phase: %0d ns",
this.ClockPeriod, 1000.0/this.ClockPeriod, this.TriggerPeriodicity, this.TriggerPhase);
endfunction
......@@ -130,6 +131,7 @@ package FfpgFmcPackage;
int Bunch;
seq_item_port.get_next_item(tx);
`uvm_info("FMCGEN", $sformatf("Parameters of the generated sequence: %s", tx.convert2string()), UVM_NONE);
if (tx.Cycles > 0)
phase.raise_objection(this);
if (tx.ClockPeriod % 2)
......
hdl/ffpg/sim/testbench/TestbenchPackage.sv
View file @ 1f9e5784
......@@ -21,9 +21,9 @@ package TestbenchPackage;
endfunction
function void write(T t);
`uvm_info("UNISUBS", $sformatf("Transaction \"%s\" received: %s", t.get_type_name(), t.convert2string()), UVM_NONE);
`uvm_info("UNISUBS", $sformatf("Transaction \"%s\" processed: %s", t.get_type_name(), t.convert2string()), UVM_NONE);
endfunction
endclass
// adopted from https://verificationacademy.com/cookbook/scoreboards
......@@ -179,8 +179,20 @@ package TestbenchPackage;
endfunction
endclass
class ReportingSequence #(type T) extends uvm_sequence #(T);
function new (string name);
super.new(name);
endfunction
virtual task pre_body();
`uvm_info("REPSEQ", $sformatf("Sequence \"%s\" is being processed: %s", this.get_type_name(), this.convert2string()), UVM_NONE);
endtask
endclass
class SeqSetDac extends uvm_sequence #(td_wb_tx);
class SeqSetDac extends ReportingSequence #(td_wb_tx);
`uvm_object_utils(SeqSetDac)
rand int VoltageRegister;
......@@ -241,7 +253,7 @@ package TestbenchPackage;
endclass
class SeqSetDelay extends uvm_sequence #(td_wb_tx);
class SeqSetDelay extends ReportingSequence #(td_wb_tx);
`uvm_object_utils(SeqSetDelay)
typedef enum {CH1_SET, CH1_RESET, CH2_SET, CH2_RESET} t_Output;
......@@ -258,6 +270,10 @@ package TestbenchPackage;
super.new(name);
endfunction
function string convert2string;
return $sformatf("Setting of delay for output %0d: delay = %0d (0x%H), repeat count = %0d.", this.ActiveOutput, this.Delay, this.Delay, this.RepeatCount);
endfunction
task body;
td_wb_tx tx;
bit busy = 0;
......@@ -306,7 +322,7 @@ package TestbenchPackage;
endclass
class SeqSetChannel extends uvm_sequence #(td_wb_tx);
class SeqSetChannel extends ReportingSequence #(td_wb_tx);
`uvm_object_utils(SeqSetChannel)
rand int Channel;
......@@ -332,6 +348,10 @@ package TestbenchPackage;
super.new(name);
endfunction
function string convert2string;
return $sformatf("Setting for channel %0d: overflow = %0d (0x%H), trigger latency = %0d (0x%H).", this.Channel, this.Overflow, this.Overflow, this.TriggerLatency, this.TriggerLatency);
endfunction
task body;
td_wb_tx tx;
int SetMemBaseAddress = (Channel == 1) ? `GET_WB_WORD_ADDR(`BASE_FFPG_CH1_SET_MEM) : `GET_WB_WORD_ADDR(`BASE_FFPG_CH2_SET_MEM);
......@@ -386,7 +406,7 @@ package TestbenchPackage;
endclass
class SeqStartChannel extends uvm_sequence #(td_wb_tx);
class SeqStartChannel extends ReportingSequence #(td_wb_tx);
`uvm_object_utils(SeqStartChannel)
rand int Channel;
......@@ -399,6 +419,10 @@ package TestbenchPackage;
super.new(name);
endfunction
function string convert2string;
return $sformatf("Starting channel %0d.", this.Channel);
endfunction
task body;
td_wb_tx tx;
int Position = (Channel == 1) ? `FFPG_CONTROL_CH1_MODE_OFFSET : `FFPG_CONTROL_CH2_MODE_OFFSET;
......@@ -415,13 +439,17 @@ package TestbenchPackage;
endclass
class SeqGenerateBeamSignals extends uvm_sequence #(FfpgFmcDriverTransaction);
class SeqGenerateBeamSignals extends ReportingSequence #(FfpgFmcDriverTransaction);
`uvm_object_utils(SeqGenerateBeamSignals)
function new (string name = "");
super.new(name);
endfunction
function string convert2string;
return "Beam signal is being generated.";
endfunction
task body;
FfpgFmcDriverTransaction tx;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment