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FMC DEL 1ns 2cha
Commit 14d21f81 authored by Jan Pospisil's avatar Jan Pospisil
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used record from ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd for WB… 

used record from ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd for WB signals in whole design
parent afca3a4c
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hdl/ffpg/rtl/FfpgCore.vhd
View file @ 14d21f81
-- TODO:
-- - use record from ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd for WB signals
-- - automatic clock infrastructure configuration
-- - clock selection
-- - clock divider
......@@ -21,8 +20,10 @@ entity FfpgCore is
);
port (
-- Wishbone connection
Wb_i: in t_WbInterfaceMosi;
Wb_o: out t_WbInterfaceMiso;
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
--- FMC interface
-- clock
ClkIn0_ik: in std_logic;
......@@ -98,10 +99,6 @@ architecture syn of FfpgCore is
signal CnxSlaveOut: t_wishbone_slave_out_array(c_NumWbMasters-1 downto 0);
signal CnxSlaveIn: t_wishbone_slave_in_array(c_NumWbMasters-1 downto 0);
-- slave WB records
signal WbMosi: t_WbInterfaceMosi;
signal WbMiso: t_WbInterfaceMiso;
begin
----------------------------------
......@@ -118,8 +115,8 @@ begin
g_sdb_addr => c_SdbAddress
)
port map (
clk_sys_i => Wb_i.Clk,
rst_n_i => not Wb_i.Rst,
clk_sys_i => Clk_ik,
rst_n_i => not Reset_ir,
slave_i => CnxSlaveIn,
slave_o => CnxSlaveOut,
master_i => CnxMasterIn,
......@@ -129,47 +126,22 @@ begin
----------------------------------
-- WB Master connection
----------------------------------
CnxSlaveIn(c_MasterId).cyc <= Wb_i.Cyc;
CnxSlaveIn(c_MasterId).stb <= Wb_i.Stb;
CnxSlaveIn(c_MasterId).adr <= Wb_i.Adr_b32;
CnxSlaveIn(c_MasterId).sel <= Wb_i.Sel_b4;
CnxSlaveIn(c_MasterId).we <= Wb_i.We;
CnxSlaveIn(c_MasterId).dat <= Wb_i.Dat_b32;
Wb_o.Ack <= CnxSlaveOut(c_MasterId).ack;
Wb_o.Err <= CnxSlaveOut(c_MasterId).err;
Wb_o.Rty <= CnxSlaveOut(c_MasterId).rty;
Wb_o.Stall <= CnxSlaveOut(c_MasterId).stall;
-- CnxSlaveOut(c_MasterId).int;
Wb_o.Dat_b32 <= CnxSlaveOut(c_MasterId).dat;
CnxSlaveIn(c_MasterId) <= Wb_i;
Wb_o <= CnxSlaveOut(c_MasterId);
----------------------------------
-- FFPG slave
----------------------------------
WbMosi.Clk <= Wb_i.Clk;
WbMosi.Rst <= Wb_i.Rst;
WbMosi.Adr_b32 <= CnxMasterOut(c_SlaveFfpgId).adr;
WbMosi.Dat_b32 <= CnxMasterOut(c_SlaveFfpgId).dat;
WbMosi.Cyc <= CnxMasterOut(c_SlaveFfpgId).cyc;
WbMosi.Sel_b4 <= CnxMasterOut(c_SlaveFfpgId).sel;
WbMosi.Stb <= CnxMasterOut(c_SlaveFfpgId).stb;
WbMosi.We <= CnxMasterOut(c_SlaveFfpgId).we;
CnxMasterIn(c_SlaveFfpgId).ack <= WbMiso.Ack;
CnxMasterIn(c_SlaveFfpgId).err <= WbMiso.Err;
CnxMasterIn(c_SlaveFfpgId).rty <= WbMiso.Rty;
CnxMasterIn(c_SlaveFfpgId).stall <= WbMiso.Stall;
CnxMasterIn(c_SlaveFfpgId).int <= '0';
CnxMasterIn(c_SlaveFfpgId).dat <= WbMiso.Dat_b32;
cFfpgSlave: entity work.FfpgSlave(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Wb_i => WbMosi,
Wb_o => WbMiso,
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Wb_i => CnxMasterOut(c_SlaveFfpgId),
Wb_o => CnxMasterIn(c_SlaveFfpgId),
ClkIn0_ik => ClkIn0_ik,
TriggerDac_o => TriggerDac_o,
VcxoDac_o => VcxoDac_o,
......
hdl/ffpg/rtl/FfpgPkg.vhd
View file @ 14d21f81
......@@ -16,25 +16,6 @@ package FfpgPkg is
SerialData => '0'
);
type t_WbInterfaceMosi is record
Clk: std_logic;
Rst: std_logic;
Adr_b32: std_logic_vector(31 downto 0);
Dat_b32: std_logic_vector(31 downto 0);
Cyc: std_logic;
Sel_b4: std_logic_vector(3 downto 0);
Stb: std_logic;
We: std_logic;
end record;
type t_WbInterfaceMiso is record
Dat_b32: std_logic_vector(31 downto 0);
Ack: std_logic;
Err: std_logic;
Rty: std_logic;
Stall: std_logic;
end record;
type t_Mode is (
e_ModeStop,
e_ModeContinuous,
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ 14d21f81
......@@ -4,6 +4,7 @@ use ieee.numeric_std.all;
use work.FfpgPkg.all;
use work.ffpg_wbgen2_pkg.all;
use work.wishbone_pkg.all;
entity FfpgSlave is
generic (
......@@ -11,8 +12,10 @@ entity FfpgSlave is
);
port (
-- Wishbone connection
Wb_i: in t_WbInterfaceMosi;
Wb_o: out t_WbInterfaceMiso;
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
--- FMC interface
-- clock
ClkIn0_ik: in std_logic;
......@@ -38,8 +41,6 @@ end entity;
architecture syn of FfpgSlave is
signal Clk, Reset: std_logic;
signal SerialStreamClock: std_logic;
signal Ch1SetMemAddress_b11: unsigned(10 downto 0);
......@@ -60,9 +61,6 @@ architecture syn of FfpgSlave is
begin
Clk <= Wb_i.Clk;
Reset <= Wb_i.Rst;
SerialStreamClock <= ClkIn0_ik;
----------------------------------
......@@ -70,6 +68,8 @@ begin
----------------------------------
cWbSlaveWrapper: entity work.WbSlaveWrapper(syn)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Wb_i => Wb_i,
Wb_o => Wb_o,
SerialStreamClock_i => SerialStreamClock,
......@@ -97,8 +97,8 @@ begin
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk,
Reset_ir => Reset,
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
TriggerValue_ib16 => WbRegsOutput.trigger_threshold_o,
TriggerLoad_i => WbRegsOutput.trigger_threshold_load_o,
VcxoValue_ib16 => WbRegsOutput.vcxo_voltage_o,
......@@ -117,8 +117,8 @@ begin
CLK_FREQ => real(g_ClkFrequency)*1.0e6
)
port map (
clk => Clk,
reset => Reset,
clk => Clk_ik,
reset => Reset_ir,
ch1_set_value => WbRegsOutput.ch1_delay_set_o,
ch1_set_load => WbRegsOutput.ch1_delay_set_load_o,
ch1_reset_value => WbRegsOutput.ch1_delay_reset_o,
......@@ -148,8 +148,8 @@ begin
----------------------------------
cDelayedPulseGeneratorCh1: entity work.DelayedPulseGenerator(syn)
port map (
Clk_ik => Clk,
Reset_ir => Reset,
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Trigger_i => Trigger_i,
SetMemAddress_ob11 => Ch1SetMemAddress_b11,
SetMemData_ib32 => Ch1SetMemData_b32,
......@@ -171,8 +171,8 @@ begin
cDelayedPulseGeneratorCh2: entity work.DelayedPulseGenerator(syn)
port map (
Clk_ik => Clk,
Reset_ir => Reset,
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Trigger_i => Trigger_i,
SetMemAddress_ob11 => Ch2SetMemAddress_b11,
SetMemData_ib32 => Ch2SetMemData_b32,
......
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ 14d21f81
......@@ -4,11 +4,14 @@ use ieee.numeric_std.all;
use work.FfpgPkg.all;
use work.ffpg_wbgen2_pkg.all;
use work.wishbone_pkg.all;
entity WbSlaveWrapper is
port (
Wb_i: in t_WbInterfaceMosi;
Wb_o: out t_WbInterfaceMiso;
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
SerialStreamClock_i: in std_logic;
Ch1SetMemAddress_ib11: in unsigned(10 downto 0);
Ch1SetMemData_ob32: out unsigned(31 downto 0);
......@@ -63,17 +66,17 @@ begin
cWbSlave: entity work.ffpg_csr(syn)
port map (
rst_n_i => not Wb_i.Rst,
clk_sys_i => Wb_i.Clk,
wb_adr_i => Wb_i.Adr_b32(13 downto 0),
wb_dat_i => Wb_i.Dat_b32,
wb_dat_o => Wb_o.Dat_b32,
wb_cyc_i => Wb_i.Cyc,
wb_sel_i => Wb_i.Sel_b4,
wb_stb_i => Wb_i.Stb,
wb_we_i => Wb_i.We,
wb_ack_o => Wb_o.Ack,
wb_stall_o => Wb_o.Stall,
rst_n_i => not Reset_ir,
clk_sys_i => Clk_ik,
wb_adr_i => Wb_i.adr(13 downto 0),
wb_dat_i => Wb_i.dat,
wb_dat_o => Wb_o.dat,
wb_cyc_i => Wb_i.cyc,
wb_sel_i => Wb_i.sel,
wb_stb_i => Wb_i.stb,
wb_we_i => Wb_i.we,
wb_ack_o => Wb_o.ack,
wb_stall_o => Wb_o.stall,
serial_stream_clk_ik => SerialStreamClock_i,
ffpg_ch1_set_mem_addr_i => std_logic_vector(Ch1SetMemAddress_ib11),
unsigned(ffpg_ch1_set_mem_data_o) => Ch1SetMemData_ob32,
......@@ -90,12 +93,13 @@ begin
regs_i => WbRegsInput,
regs_o => WbRegsOutput
);
Wb_o.Err <= '0';
Wb_o.Rty <= '0';
Wb_o.err <= '0';
Wb_o.rty <= '0';
Wb_o.int <= '0';
-- local registers for LOAD_EXT fields
pLocalRegs: process (Wb_i.Clk) is begin
if rising_edge(Wb_i.Clk) then
pLocalRegs: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
control_clock_selection_load <= '0';
control_ch1_mode_load <= '0';
control_ch2_mode_load <= '0';
......
hdl/ffpg/sim/testbench/FfpgCoreWrapper.vhd
View file @ 14d21f81
......@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FfpgPkg.all;
use work.wishbone_pkg.all;
entity FfpgCoreWrapper is
generic (
......@@ -23,6 +24,7 @@ entity FfpgCoreWrapper is
wb_err_o: out std_logic;
wb_rty_o: out std_logic;
wb_stall_o: out std_logic;
wb_int_o: out std_logic;
ClkIn0_ik: in std_logic;
TriggerDacFrameSynchronization_n: out std_logic;
TriggerDacSerialClock: out std_logic;
......@@ -49,25 +51,25 @@ architecture syn of FfpgCoreWrapper is
signal TriggerDac: t_Ad5600Interface;
signal VcxoDac: t_Ad5600Interface;
signal WbMosi: t_WbInterfaceMosi;
signal WbMiso: t_WbInterfaceMiso;
signal WbMosi: t_wishbone_slave_in;
signal WbMiso: t_wishbone_slave_out;
begin
WbMosi.Clk <= clk_sys_i;
WbMosi.Rst <= rst_i;
WbMosi.Adr_b32 <= wb_adr_i;
WbMosi.Dat_b32 <= wb_dat_i;
WbMosi.Cyc <= wb_cyc_i;
WbMosi.Sel_b4 <= wb_sel_i;
WbMosi.Stb <= wb_stb_i;
WbMosi.We <= wb_we_i;
WbMosi.adr <= wb_adr_i;
WbMosi.dat <= wb_dat_i;
WbMosi.cyc <= wb_cyc_i;
WbMosi.sel <= wb_sel_i;
WbMosi.stb <= wb_stb_i;
WbMosi.we <= wb_we_i;
cFfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => clk_sys_i,
Reset_ir => rst_i,
Wb_i => WbMosi,
Wb_o => WbMiso,
ClkIn0_ik => ClkIn0_ik,
......@@ -87,11 +89,12 @@ begin
Trigger_i => Trigger_i
);
wb_dat_o <= WbMiso.Dat_b32;
wb_ack_o <= WbMiso.Ack;
wb_err_o <= WbMiso.Err;
wb_rty_o <= WbMiso.Rty;
wb_stall_o <= WbMiso.Stall;
wb_dat_o <= WbMiso.dat;
wb_ack_o <= WbMiso.ack;
wb_err_o <= WbMiso.err;
wb_rty_o <= WbMiso.rty;
wb_stall_o <= WbMiso.stall;
wb_int_o <= WbMiso.int;
TriggerDacFrameSynchronization_n <= TriggerDac.FrameSynchronization_n;
TriggerDacSerialClock <= TriggerDac.SerialClock;
......
hdl/ffpg/sim/testbench/Testbench.sv
View file @ 14d21f81
......@@ -31,6 +31,7 @@ module Testbench;
.wb_err_o(LocalInterface.Wb.err),
.wb_rty_o(LocalInterface.Wb.rty),
.wb_stall_o(), // doesn't exist in B3 version of WB
.wb_int_o(), // doesn't exist in B3 version of WB
.ClkIn0_ik(LocalInterface.Fmc.ClkIn0),
.TriggerDacFrameSynchronization_n(LocalInterface.TriggerDac.FrameSynchronization_n),
.TriggerDacSerialClock(LocalInterface.TriggerDac.SerialClock),
......
hdl/ffpg/sim/testbench/make
View file @ 14d21f81
......@@ -27,6 +27,7 @@ vcom -2008 -reportprogress 300 -work work ../../rtl/Reg.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/RegSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/FfpgPkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/ffpg_csr_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/ffpg_csr.vhd
......@@ -38,7 +39,6 @@ vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/RfClkD
vcom -2008 -reportprogress 300 -work work ../../rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/FfpgSlave.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
......
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