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FMC DEL 1ns 2cha
Commit 9592d604 authored by Jan Pospisil's avatar Jan Pospisil
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fixed data delay in LOAD_EXT registers; small fixes in core

parent 0dac69eb
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Showing with 78 additions and 43 deletions
hdl/ffpg/rtl/FfpgCore.vhd
View file @ 9592d604
......@@ -54,7 +54,7 @@ architecture syn of FfpgCore is
return i;
end function;
function calculateSclkDivsel(CLK_FREQ, DAC_FREQ_MAX: natural) return std_logic_vector(2 downto 0) is
function calculateSclkDivsel (CLK_FREQ, DAC_FREQ_MAX: natural) return std_logic_vector is
variable result: integer;
begin
result := f_log2(CLK_FREQ/DAC_FREQ_MAX);
......@@ -63,6 +63,9 @@ architecture syn of FfpgCore is
else
result := result - 3;
end if;
assert result < 8
report "Clock frequency is too high for use with module gc_serial_dac!"
severity failure;
return std_logic_vector(to_unsigned(result, 3));
end function;
......@@ -89,7 +92,8 @@ architecture syn of FfpgCore is
signal Ch2SetMem: t_ChannelMemory;
signal Ch2ResMem: t_ChannelMemory;
-- extension to WB slave - registers for LOAD_EXT fields
---- extension to WB slave
-- registers for LOAD_EXT fields
signal control_clock_selection: std_logic_vector(1 downto 0);
signal control_ch1_mode: std_logic_vector(1 downto 0);
signal control_ch2_mode: std_logic_vector(1 downto 0);
......@@ -101,18 +105,26 @@ architecture syn of FfpgCore is
signal ch2_delay_reset: std_logic_vector(9 downto 0);
signal trigger_register: std_logic_vector(15 downto 0);
signal overflow: std_logic_vector(15 downto 0);
-- delayed load signals
signal control_clock_selection_load: std_logic;
signal control_ch1_mode_load: std_logic;
signal control_ch2_mode_load: std_logic;
signal vcxo_register_load: std_logic;
signal clock_divider_hi_load: std_logic;
signal ch1_delay_set_load: std_logic;
signal ch1_delay_reset_load: std_logic;
signal ch2_delay_set_load: std_logic;
signal ch2_delay_reset_load: std_logic;
signal trigger_register_load: std_logic;
signal overflow_load: std_logic;
begin
assert SCLK_DIVSEL < 8
report "Clock frequency is too high for use with module gc_serial_dac!"
severity failure;
cWbSlave: entity work.ffpg_csr(syn)
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_adr_i,
wb_adr_i => wb_adr_i(13 downto 0),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
......@@ -140,39 +152,62 @@ begin
process (clk_sys_i) is begin
if rising_edge(clk_sys_i) then
control_clock_selection_load <= '0';
control_ch1_mode_load <= '0';
control_ch2_mode_load <= '0';
vcxo_register_load <= '0';
clock_divider_hi_load <= '0';
ch1_delay_set_load <= '0';
ch1_delay_reset_load <= '0';
ch2_delay_set_load <= '0';
ch2_delay_reset_load <= '0';
trigger_register_load <= '0';
overflow_load <= '0';
if WbRegsOutput.control_clock_selection_load_o then
control_clock_selection <= WbRegsOutput.control_clock_selection_o
end if
control_clock_selection <= WbRegsOutput.control_clock_selection_o;
control_clock_selection_load <= '1';
end if;
if WbRegsOutput.control_ch1_mode_load_o then
control_ch1_mode <= WbRegsOutput.control_ch1_mode_o
end if
control_ch1_mode <= WbRegsOutput.control_ch1_mode_o;
control_ch1_mode_load <= '1';
end if;
if WbRegsOutput.control_ch2_mode_load_o then
control_ch2_mode <= WbRegsOutput.control_ch2_mode_o
end if
control_ch2_mode <= WbRegsOutput.control_ch2_mode_o;
control_ch2_mode_load <= '1';
end if;
if WbRegsOutput.vcxo_register_load_o then
vcxo_register <= WbRegsOutput.vcxo_register_o
end if
vcxo_register <= WbRegsOutput.vcxo_register_o;
vcxo_register_load <= '1';
end if;
if WbRegsOutput.clock_divider_hi_load_o then
clock_divider_hi <= WbRegsOutput.clock_divider_hi_o
end if
clock_divider_hi <= WbRegsOutput.clock_divider_hi_o;
clock_divider_hi_load <= '1';
end if;
if WbRegsOutput.ch1_delay_set_load_o then
ch1_delay_set <= WbRegsOutput.ch1_delay_set_o
end if
ch1_delay_set <= WbRegsOutput.ch1_delay_set_o;
ch1_delay_set_load <= '1';
end if;
if WbRegsOutput.ch1_delay_reset_load_o then
ch1_delay_reset <= WbRegsOutput.ch1_delay_reset_o
end if
ch1_delay_reset <= WbRegsOutput.ch1_delay_reset_o;
ch1_delay_reset_load <= '1';
end if;
if WbRegsOutput.ch2_delay_set_load_o then
ch2_delay_set <= WbRegsOutput.ch2_delay_set_o
end if
ch2_delay_set <= WbRegsOutput.ch2_delay_set_o;
ch2_delay_set_load <= '1';
end if;
if WbRegsOutput.ch2_delay_reset_load_o then
ch2_delay_reset <= WbRegsOutput.ch2_delay_reset_o
end if
ch2_delay_reset <= WbRegsOutput.ch2_delay_reset_o;
ch2_delay_reset_load <= '1';
end if;
if WbRegsOutput.trigger_register_load_o then
trigger_register <= WbRegsOutput.trigger_register_o
end if
trigger_register <= WbRegsOutput.trigger_register_o;
trigger_register_load <= '1';
end if;
if WbRegsOutput.overflow_load_o then
overflow <= WbRegsOutput.overflow_o
end if
overflow <= WbRegsOutput.overflow_o;
overflow_load <= '1';
end if;
end if;
end process;
WbRegsInput.control_clock_selection_i <= control_clock_selection;
......@@ -187,24 +222,24 @@ begin
WbRegsInput.trigger_register_i <= trigger_register;
WbRegsInput.overflow_i <= overflow;
TriggerDacEn <= WbRegsOutput.trigger_register_load_o and not WbRegsInput.status_dac_trigger_busy_i;
VcxoDacEn <= WbRegsOutput.vcxo_register_load_o and not WbRegsInput.status_dac_vcxo_busy_i;
TriggerDacEn <= trigger_register_load and not WbRegsInput.status_dac_trigger_busy_i;
VcxoDacEn <= vcxo_register_load and not WbRegsInput.status_dac_vcxo_busy_i;
cTriggerDac: entity work.gc_serial_dac(syn)
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0,
g_sclk_polarity => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
value_i => trigger_register,
cs_sel_i => TriggerDacEn,
cs_sel_i(0) => TriggerDacEn,
load_i => TriggerDacEn,
sclk_divsel_i => SCLK_DIVSEL,
dac_cs_n_o => TriggerDac_o.FrameSynchronization_n,
dac_cs_n_o(0) => TriggerDac_o.FrameSynchronization_n,
dac_sclk_o => TriggerDac_o.SerialClock,
dac_sdata_o => TriggerDac_o.SerialData,
busy_o => WbRegsInput.status_dac_trigger_busy_i
......@@ -215,16 +250,16 @@ begin
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0,
g_sclk_polarity => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
value_i => vcxo_register,
cs_sel_i => VcxoDacEn,
cs_sel_i(0) => VcxoDacEn,
load_i => VcxoDacEn,
sclk_divsel_i => SCLK_DIVSEL,
dac_cs_n_o => VcxoDac_o.FrameSynchronization_n,
dac_cs_n_o(0) => VcxoDac_o.FrameSynchronization_n,
dac_sclk_o => VcxoDac_o.SerialClock,
dac_sdata_o => VcxoDac_o.SerialData,
busy_o => WbRegsInput.status_dac_vcxo_busy_i
......@@ -234,13 +269,13 @@ begin
ch2_out_en <= WbRegsOutput.control_ch2_oe_o;
-- WbRegsOutput.clock_divider_lo_o
WbRegsInput.status_clock_infrastructure_busy_i <= 'x';
WbRegsInput.status_clock_selection_busy_i <= 'x';
WbRegsInput.status_delay_configuration_busy_i <= 'x';
WbRegsInput.status_clock_infrastructure_busy_i <= 'X';
WbRegsInput.status_clock_selection_busy_i <= 'X';
WbRegsInput.status_delay_configuration_busy_i <= 'X';
WbRegsInput.status_channel_1_oe_i <= WbRegsOutput.control_ch1_oe_o;
WbRegsInput.status_channel_2_oe_i <= WbRegsOutput.control_ch2_oe_o;
WbRegsInput.status_channel_1_running_i <= 'x';
WbRegsInput.status_channel_2_running_i <= 'x';
WbRegsInput.status_channel_1_running_i <= 'X';
WbRegsInput.status_channel_2_running_i <= 'X';
WbRegsInput.frequency_i <= (others => 'X');
end architecture;
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