- 21 Dec, 2016 1 commit
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Denia Bouhired-Ferrag authored
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- 20 Dec, 2016 5 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Modified conv_regs entity and component declaration according to new conv_regs.vhd from previous commit
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Denia Bouhired-Ferrag authored
conv_regs.vhd had some minor inconsistencies with conv_regs.wb due to some manual changes. conv_regs.wb has now been modified to match a more recent one on remotes/origin/wr-n-th and then conv_regs has been regenerated without manual intervention
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 19 Dec, 2016 1 commit
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Denia Bouhired-Ferrag authored
Small modifications to account for very short pulses of 250ns. Previously module would not work properly for the required 2MHz frequency
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- 16 Dec, 2016 3 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 12 Dec, 2016 1 commit
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Denia Bouhired-Ferrag authored
Updated top file and burt control module with little modifications. NOTE LED sequence is fixed at certain pattern for bitstream debugging
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- 07 Dec, 2016 4 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Modified top files to support all modifications in register map plus the new burst controller. Note that the burst controller supported in this commit is the one that averages frequency over 1000 pulses
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 07 Sep, 2016 1 commit
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Denia Bouhired-Ferrag authored
Added new registers to count TTL pulses and Blocking pulses separately for each channel, instead of counting the OR of the two
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- 10 Aug, 2016 1 commit
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Denia Bouhired-Ferrag authored
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- 05 Aug, 2016 1 commit
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Denia Bouhired-Ferrag authored
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- 11 Dec, 2014 3 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
The description of the CSR.RST bit has been made clearer to show that it is only active when CSR.RST_UNLOCK = '1'.
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Theodor-Adrian Stana authored
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- 26 Sep, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 25 Sep, 2014 1 commit
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Theodor-Adrian Stana authored
OSWR also now contains 32 bits, to allow for 32 switches in addition to the existing 8 general-purpose ones.
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- 24 Sep, 2014 1 commit
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Theodor-Adrian Stana authored
The 125 MHz domain registers are loaded only once the 20 MHz clock domain registers are loaded. Like this, we avoid having different values in the registers in the two clock domains.
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- 29 Aug, 2014 6 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
This makes the doc and module more generic. The modification will be made in the code as well.
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Theodor-Adrian Stana authored
Also added link to OHWR Wiki page for project examples in the same section.
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- 25 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
This is to make sure no readouts of erroneous values from this registers occur due to the register value not being stable at the time the WB read cycle is requested.
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- 22 Aug, 2014 4 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
The pulse synchronizer for the latest timestamp load signal implemented as part of the previous commit was not working, due to a wrongly-connected signal. The appropriate signal was connected and the pulse synchronization mechanism seems to work.
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Theodor-Adrian Stana authored
The pulse synchronizer makes sure the load pulse to the 125 MHz clock domain registers generates a pulse to load the registers in the 20 MHz clock domain, which are the registers that are read via I2C.
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- 21 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
The sys err port also activates on PMISSE errors from any channels, which was an omission in the previous commits, since I was working mainly on the RS-485 repeater. Now, the interface is clearer and easier to use. Just connect led_syserr_o to the ERR bicolor LED on the board.
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- 20 Aug, 2014 2 commits
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Theodor-Adrian Stana authored
The memory map has been updated to include the thermometer SDB descriptor. Appendix B was added, containing guidelines on how to implement a pulse repeater with more than six channels.
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Theodor-Adrian Stana authored
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- 18 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
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