1.1.1 - 2020-09-14
==================

Fixed
-----
- sw: fix SPI driver to update the spi_message->actual_length

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

The spi-ocore driver was not updating the actual_length field in the
spi_message structure. This field could be used by SPI users to see if
all bytes have been transferred.

In particular we found the problem because the m25p80 driver uses the
actual_length to determine if there are transmission errors (-EIO).
Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

The response should not be EXOKAY unless an atomic access is requested
by the master using the LOCK signals.  This bridge does not even
support atomic accesses (it's an AXI4-Lite slave and does not have the
LOCK signals) so it's required to respond OKAY even if the master
does attempt an atomic access (this is how the master knows that the
slave does not support atomic accesses).  The AXI4-Lite specification
clearly states that the EXOKAY response is not supported in AXI4-Lite.

The BVALID signal must be asserted once the write operation is
completed.  The master is not required to assert BREADY before this
happens.  The old code happened to work if the master tied BREADY
high, which is allowed but not required.

Conflicts:
	modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd

wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed together

1.1.0 - 2020-07-24
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.0

Added
-----
- hdl: New indirect wishbone master (driven by an address and data register).
- hdl: New memory wrapper for Cheby.
- hdl: Provide a simple vhdl package to generate WB transactions.
- hdl: New wb_xc7_fw_update module.
- bld: Introduce gen_sourceid.py script to generate a package with the source id.

Changed
-------
- bld: gen_buildinfo.py now adds tag and dirty flag.

Fixed
-----
- hdl: regression to gc_sync_ffs introduced by v1.0.4.
- hdl: add dummy generic to generic_dpram in altera.
- hdl: add missing generics to generic_sync_fifo in genram_pkg.
- hdl: avoid f_log2() circular dependencies in gc_extend_pulse.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Previously, the full flag was asserted at g_size-1 when using g_show_ahead.
The new implementation solves this. However, for backward compatibility,
the default is to still use the previous behaviour. Set g_show_ahead_legacy_mode
to false to switch to the new one.

As a generic module to update xc7 firmware.

Used for fpga-dev-id (aka the convention).

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This bugfix has been tested by myself on the latest development version of SPEC-based FMC-ADC, as
well as by M. Lipinski on BTrain test setup.

Closes #23.

The only reason for this is to improve readability and reduce the usage of gc_posedge/gc_negedge, in
case we want to deprecate them in the near future.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

The main reason for doing this is so that all our sync modules are based directly on
gc_sync (instead of using it indirectly through gc_sync_ffs).

Another benefit of this is that the feedback loop of the pulse synchroniser will now be two clock
cycles shorter (one input clock cycle + one output clock cycle), since gc_sync_ffs is using one
more flip-flop compared to gc_sync.

This will also reduce the number of warnings in various synthesis and simulation tools, since
gc_pulse_syncrhonizer is also used by the gc_sync_word modules, as well as the async dual clock
FIFOs.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>