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Platform-independent core collection
Commit 2894aa01 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tristan Gingold
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wb_simple_uart: allow preset baudrate register through a generic

parent 9ca6d7d2
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Showing with 9 additions and 5 deletions
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 2894aa01
......@@ -42,7 +42,8 @@ entity wb_simple_uart is
g_WITH_PHYSICAL_UART : boolean;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0
);
port (
......@@ -161,8 +162,8 @@ begin -- arch
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
uart_bcr <= (others => '0');
elsif regs_out.bcr_wr_o = '1' then
uart_bcr <= std_logic_vector(to_unsigned(g_preset_bcr, uart_bcr'length));
elsif(regs_out.bcr_wr_o = '1')then
uart_bcr <= regs_out.bcr_o;
end if;
end if;
......
modules/wishbone/wb_uart/xwb_simple_uart.vhd
View file @ 2894aa01
......@@ -41,7 +41,9 @@ entity xwb_simple_uart is
g_WITH_PHYSICAL_UART : boolean := TRUE;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024);
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0
);
port (
clk_sys_i : in std_logic;
......@@ -68,7 +70,8 @@ begin -- arch
g_WITH_PHYSICAL_UART => g_WITH_PHYSICAL_UART,
g_INTERFACE_MODE => g_INTERFACE_MODE,
g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY,
g_VUART_FIFO_SIZE => g_VUART_FIFO_SIZE)
g_VUART_FIFO_SIZE => g_VUART_FIFO_SIZE,
g_PRESET_BCR => g_PRESET_BCR)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
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