Commits · 9393a482fb4f03f31c95b7972fe783b410f0cb65 · Projects / FMC DEL 1ns 2cha

28 Jul, 2016 2 commits
- vme64x-core submodule added · 9393a482
  Jan Pospisil authored Jul 28, 2016
  
  9393a482
- name style fix · a7ade948
  Jan Pospisil authored Jul 28, 2016
  
  a7ade948
27 Jul, 2016 2 commits
- added UCF constraint file - implementation flow works (result is not tested) · b008376f
  Jan Pospisil authored Jul 27, 2016
  
  b008376f
- added glue logic to the SVEC top level entity SvecTopFfpg.vhd (inspired by… · 1a629ebc
  Jan Pospisil authored Jul 27, 2016
```
added glue logic to the SVEC top level entity SvecTopFfpg.vhd (inspired by git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git)
```
  1a629ebc
26 Jul, 2016 6 commits
- added ignore for ISE project · e58c9532
  Jan Pospisil authored Jul 26, 2016
  
  e58c9532
- added SVEC synthesis top file and ISE project; fixed code for unsupported VHDL 2008 · ff02b113
  Jan Pospisil authored Jul 26, 2016
  
  ff02b113
- added 1-wire temperature module · 80a91b70
  Jan Pospisil authored Jul 26, 2016
  
  80a91b70
- temporary solution for clock selection · 3c803047
  Jan Pospisil authored Jul 26, 2016
  
  3c803047
- added AD9512 SPI module · 64f55ee8
  Jan Pospisil authored Jul 26, 2016
  
  64f55ee8
- used record from ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd for WB… · 14d21f81
  Jan Pospisil authored Jul 26, 2016
```
used record from ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd for WB signals in whole design
```
  14d21f81
25 Jul, 2016 6 commits
- added WB SDB crossbar · afca3a4c
  Jan Pospisil authored Jul 25, 2016
  
  afca3a4c
- added one layer in the hierarchy (FfpgCore -> FfpgSlave) to make space for other WB sub-slaves · 0981397c
  Jan Pospisil authored Jul 25, 2016
  
  0981397c
- fixed gap in serial stream generation · b6aa96d7
  Jan Pospisil authored Jul 25, 2016
  
  b6aa96d7
- fixed simulation to prevent cases Overflow > TriggerPeriodicity · 525e4dd7
  Jan Pospisil authored Jul 25, 2016
  
  525e4dd7
- reporting improved · 1f9e5784
  Jan Pospisil authored Jul 25, 2016
  
  1f9e5784
- workaround for ModelSim SIGSEGV bug · ab21bab9
  Jan Pospisil authored Jul 25, 2016
  
  ab21bab9
06 Jul, 2016 3 commits
- added test for external clock pulse generation - not simulated, not tested… · afc216d5
  Jan Pospisil authored Jul 06, 2016
```
added test for external clock pulse generation - not simulated, not tested (ModelSim 10.4d crashing)
```
  afc216d5
- added CDCs for DelayedPulseGenerator (not yet tested!) · fd39fcad
  Jan Pospisil authored Jul 06, 2016
  
  fd39fcad
- added RegSyncer entity for CDC of vectors · 5ecace74
  Jan Pospisil authored Jul 06, 2016
  
  5ecace74
05 Jul, 2016 3 commits
- modified code to use separate domain clock for serial stream generation (not finished yet) · 2ec6d762
  Jan Pospisil authored Jul 05, 2016
  
  2ec6d762
- added "set feature" to Counter entity · 7faf3e2c
  Jan Pospisil authored Jul 05, 2016
  
  7faf3e2c
- consolidated Counter and CounterO entities into Counter and CounterLength, added testbench · 58e87754
  Jan Pospisil authored Jul 05, 2016
  
  58e87754
04 Jul, 2016 5 commits
- added trigger latency specification (not implemented yet); renamed some WB… · a4f3e56c
  Jan Pospisil authored Jul 04, 2016
```
added trigger latency specification (not implemented yet); renamed some WB registers to better reflect it purpose
```
  a4f3e56c
- added basic test for pulse generation · 9e19b2b1
  Jan Pospisil authored Jul 04, 2016
  
  9e19b2b1
- added code for pulse generation - only continuous mode implemented, not tested · e728dc75
  Jan Pospisil authored Jul 04, 2016
  
  e728dc75
- changed some SLV to UNSIGNED · 35d5e2a7
  Jan Pospisil authored Jul 04, 2016
  
  35d5e2a7
- added skeleton for pulse generation code · 63c67489
  Jan Pospisil authored Jul 04, 2016
  
  63c67489
01 Jul, 2016 4 commits
- moved Wishbone code to separate entity; typos · a15dd5d0
  Jan Pospisil authored Jul 01, 2016
  
  a15dd5d0
- moved DAC controlling code to separate entity; renamed main package to be project-wide · 18bc97c2
  Jan Pospisil authored Jul 01, 2016
  
  18bc97c2
- separated registers for delay configuration (for better operability); added… · 6b8921d4
  Jan Pospisil authored Jul 01, 2016
```
separated registers for delay configuration (for better operability); added basic testbench for "delay configuration"; fixed few bugs around delay configuration; used WBGEN2 generated Verilog constant file for simulation; typos
```
  6b8921d4
- added delay configuration RTL (not tested) · 5bf2f339
  Jan Pospisil authored Jul 01, 2016
  
  5bf2f339
30 Jun, 2016 3 commits
- added full-zoom after-simulation command · 7e9e5fa7
  Jan Pospisil authored Jun 30, 2016
  
  7e9e5fa7
- added UVM testbench suite; typos · 22bad477
  Jan Pospisil authored Jun 30, 2016
  
  22bad477
- fixed data delay in LOAD_EXT registers; small fixes in core · 9592d604
  Jan Pospisil authored Jun 30, 2016
  
  9592d604
28 Jun, 2016 4 commits
- added blind signals to make syntax-OK file · 0dac69eb
  Jan Pospisil authored Jun 28, 2016
  
  0dac69eb
- WIP: added first draft of top-level module for FFPG · f98dfd7f
  Jan Pospisil authored Jun 28, 2016
  
  f98dfd7f
- finished RC1 version of WB slave definition; added sub-modules (wishbone-gen, general-cores) · b3e15c8c
  Jan Pospisil authored Jun 28, 2016
  
  b3e15c8c
- initial commit, first few files · 44dc14fe
  Jan Pospisil authored Jun 28, 2016
  
  44dc14fe