Commit b3e15c8c authored by Jan Pospisil's avatar Jan Pospisil

finished RC1 version of WB slave definition; added sub-modules (wishbone-gen, general-cores)

parent 44dc14fe
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "hdl/ip_cores/wishbone-gen"]
path = hdl/ip_cores/wishbone-gen
url = git://ohwr.org/hdl-core-lib/wishbone-gen.git
files = [
"ffpg_csr.vhd",
"ffpg_csr_pkg.vhd"]
modules = { "local" : ["../../ip_cores/wishbone-gen/lib"]}
WBGEN2=wbgen2
RTL=../rtl/
TEX=../../../doc/manual/
%:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
\ No newline at end of file
......@@ -298,11 +298,34 @@ peripheral {
access_dev = READ_ONLY;
};
ram {
name = "CH1 RES serial stream";
prefix = "ch1_res_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
ram {
name = "CH2 SET serial stream";
prefix = "ch2_set_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
ram {
name = "CH2 RES serial stream";
prefix = "ch2_res_mem";
width = 32;
size = 2048;
clock = "serial_stream_clk_ik";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
general-cores @ bd7bca1c
Subproject commit bd7bca1cfb18346c2f4d42f7b5d94a79d7657117
wishbone-gen @ 8d431e7f
Subproject commit 8d431e7f4dbd9e2423b3207267c7495df64e27b0
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