description = "Pulse generator channel 1 running\n0: channel 1 is not running\n1: channel 1 is running, pulses are generated";
prefix = "channel_1_running";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Pulse generator channel 2 running";
description = "Pulse generator channel 2 running\n0: channel 2 is not running\n1: channel 2 is running, pulses are generated";
prefix = "channel_2_running";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control register";
prefix = "control";
field {
name = "Clock source selection";
description = "0 (default): external clock used (connector on the front panel)\n1: FPGA loop clock used\n2: onboard clock used";
prefix = "clock_selection";
type = SLV;
size = 2;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "CH1 output enable";
prefix = "ch1_oe";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "CH2 output enable";
prefix = "ch2_oe";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "CH1 mode selection";
description = "0 (default): stopped (no output generated)\n1: continuous (non-stop memory looping)\n2: one-shot (loop memory just once)";
prefix = "ch1_mode";
type = SLV;
size = 2;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "CH2 mode selection";
description = "0 (default): stopped (no output generated)\n1: continuous (non-stop memory looping)\n2: one-shot (loop memory just once)";
prefix = "ch2_mode";
type = SLV;
size = 2;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "VCXO voltage register";
prefix = "vcxo_register";
description = "This register value D determines output voltage of the VCXO DAC.\nVoltage should be V_OUT = D * 5 / 65536 [V] (see datasheet), but is limited by 3.3 V supply voltage of the DAC.";
field {
name = "VCXO voltage register value";
type = SLV;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Clock divider";
prefix = "clock_divider";
description = "LOw and HIgh values of the AD9512 clock divider - these values are used for all clocks generated on the FMC card. Write both values at one WB transaction, or write LO first and HI last. Clock configuration of both values begins when HI value is written.";
field {
name = "Clock divider LO value";
description = "Number of clock cycles output stays low.";
prefix = "lo";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Clock divider HI value";
description = "Number of clock cycles output stays high.";
prefix = "hi";
type = SLV;
size = 4;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "CH1 delay configuration";
prefix = "ch1_delay";
description = "10 bit fine delays for pulse generation.";
field {
name = "CH1 SET delay";
description = "Delay of the SET pulse, i.e. pulse delay.";
prefix = "set";
type = SLV;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "CH1 RES delay";
description = "Delay of the RES pulse, i.e. pulse width.";
prefix = "reset";
type = SLV;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "CH2 delay configuration";
prefix = "ch2_delay";
description = "10 bit fine delays for pulse generation.";
field {
name = "CH2 SET delay";
description = "Delay of the SET pulse, i.e. pulse delay.";
prefix = "set";
type = SLV;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "CH2 RES delay";
description = "Delay of the RES pulse, i.e. pulse width.";
prefix = "reset";
type = SLV;
size = 10;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Trigger threshold voltage register";
prefix = "trigger_register";
description = "This register value D determines output voltage of the trigger threshold DAC.\nVoltage should be V_OUT = D * 5 / 65536 [V] (see datasheet).";
field {
name = "Trigger threshold voltage register value";
type = SLV;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Overflow";
prefix = "overflow";
description = "Overflow index for serial stream memory. When this index is reach when looping the memory, memory index is reset back to 0.";
field {
name = "Overflow value";
type = SLV;
size = 16;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Clock frequency";
prefix = "frequency";
description = "Frequency of the input clock in kHz.";
