- freq, pulse, delay controllable via ports

made the necessary changes in
- source files
- vbcp_wb doc
- hdlguide

- pulse rejection to 1/5 duty cycle
- status reg contains fwvers, switches and rtm field
- i2c_slave has internal watchdog timer

- hdl compiles fine, still needs actual testing
- changed hdlguide to reflect new folder structure due to submodule

- hdlguide: added info about pulse rejection
- userguide: corrected channel delay when glitch filt enabled (40ns ->
  56 ns)
- changed firmware version in release top-level file