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Commit 5aac9b06 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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added rtm interface tester files

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modelsim.ini.bak deleted 100644 → 0
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pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.DRL 0 → 100644
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TT#v 2 s k #v 2 sk #v 2 sk #v 2 sk # 7 8 7 8 7 7 7 8 7 7 7 7 8 7 # 7 8 7 7 7 7  7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7  7 7 7 7 7 7 7 7 7 7 8 8 8  8 7 7 7 8  7 7 8 7 7 8 7 7 7 8 8  8 7 7 8  7 8 7 8 7 7 8 8  8 7 7 7  7 8  7  7 7 8 7 7  7 8 7  7 7 7 8 8  8 7 7 7 7 7 7 8  7 7 7 7 7 8 7 7 7 7 7 8 7 7 7 7 7 7 7 8 7 8  7 8 7 7 7 7  7 7 7 7 7 7 8  7 7 7 7 7 7  7 7 8 7 7  7 7 7 7 7 7 8 7 7 7 7 7 7  7 7 7 8 8  8 7 8  8 8 # 7 8 7 # 7 8 7 7 T
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pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.DRR 0 → 100644
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---------------------------------------------------------------------------
NCDrill File Report For: RTM_Interface_Tester.PcbDoc 5/14/2013 12:53:44 PM
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : RTM_Interface_Tester.TXT
EIA File : RTM_Interface_Tester.DRL
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.5mm (19.685mil) Round 10 148.01 mm (5.83 Inch)
T2 1mm (39.37mil) Round 160 485.14 mm (19.10 Inch)
T3 2.8mm (110.236mil) Round 2 88.90 mm (3.50 Inch)
T4 3mm (118.11mil) Round 3 90.00 mm (3.54 Inch)
---------------------------------------------------------------------------
Totals 175 812.05 mm (31.97 Inch)
Total Processing Time (hh:mm:ss) : 00:00:00
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.EXTREP 0 → 100644
View file @ 5aac9b06
------------------------------------------------------------------------------------------
Gerber File Extension Report For: RTM_Interface_Tester.GBR 5/14/2013 12:53:31 PM
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL Top Layer
.GBL Bottom Layer
.GTO Top Overlay
.GTS Top Solder
.GBS Bottom Solder
.GM1 Mechanical 1
.GM7 Mechanical 7
------------------------------------------------------------------------------------------
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GBS 0 → 100644
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pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GM1 0 → 100644
View file @ 5aac9b06
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pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GM7 0 → 100644
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pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GTL 0 → 100644
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D03*
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D03*
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D03*
M02*
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GTS 0 → 100644
View file @ 5aac9b06
%FSLAX42Y42*%
%MOMM*%
G71*
G01*
G75*
G04 Layer_Color=8388736*
%ADD10R,2.15X2.30*%
%ADD11R,1.80X1.15*%
%ADD12C,1.00*%
%ADD13C,0.25*%
%ADD14C,3.00*%
%ADD15C,1.50*%
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%ADD17C,1.00*%
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%ADD19C,0.20*%
%ADD20C,0.25*%
%ADD21R,2.35X2.50*%
%ADD22R,2.00X1.35*%
%ADD23C,3.20*%
%ADD24C,1.70*%
%ADD25C,3.70*%
%ADD26C,1.20*%
D21*
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X1600Y2890D02*
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M02*
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.LDP 0 → 100644
View file @ 5aac9b06
Layer Pairs Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=rtm_interface_tester.txt|LayerPairs=gtl,gbl
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.REP 0 → 100644
View file @ 5aac9b06
*************************************************************
FileName = RTM_Interface_Tester.GBR
AutoAperture = True
*************************************************************
Generating : Top Layer
File : RTM_Interface_Tester.GTL
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
D13
D14
D15
D16
D17
*************************************************************
*************************************************************
Generating : Bottom Layer
File : RTM_Interface_Tester.GBL
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D12
D13
D14
D15
D17
D18
*************************************************************
*************************************************************
Generating : Top Overlay
File : RTM_Interface_Tester.GTO
Adding Layer : Top Overlay
Used DCodes :
D13
D19
D20
*************************************************************
*************************************************************
Generating : Top Solder
File : RTM_Interface_Tester.GTS
Adding Layer : Top Solder
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D21
D22
D23
D24
D25
D26
*************************************************************
*************************************************************
Generating : Bottom Solder
File : RTM_Interface_Tester.GBS
Adding Layer : Bottom Solder
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D23
D24
D26
D27
*************************************************************
*************************************************************
Generating : Mechanical 1
File : RTM_Interface_Tester.GM1
Adding Layer : Mechanical 1
Used DCodes :
D28
*************************************************************
*************************************************************
Generating : Mechanical 7
File : RTM_Interface_Tester.GM7
Adding Layer : Mechanical 7
Used DCodes :
*************************************************************
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.RUL 0 → 100644
View file @ 5aac9b06
DRC Rules Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
RuleKind=Width|RuleName=Width_GND|Scope=Board|Minimum=10.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width_Normal|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=6.69
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.TXT 0 → 100644
View file @ 5aac9b06
M48
;Layer_Color=9474304
;FILE_FORMAT=4:2
METRIC,LZ
;TYPE=PLATED
T1F00S00C0.50
T2F00S00C1.00
T3F00S00C2.80
T4F00S00C3.00
%
T01
X0016Y00289
X0028Y0029
X0042
X0054
X00378Y0017
X00252
X00633
X00771
X008Y0029
X0067
T02
X005688Y000277
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X00645
X006704
X006958
X007212
X007466
X00772
X007974
X008228
X008482
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X005434
X00518
X004926
X004672
X004418
X004164
X00391
X003656
X003402
X003148
X002894
X00264
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X002132
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X001624
X00137
X001116
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Y000531
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Y001039
Y001293
X001116
X00137
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X001116
X001878
Y000785
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Y000531
X00518
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Y000531
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Y000785
Y001039
Y001293
X008736
Y001039
Y000785
Y000531
T03
X009244Y000277
X000354
T04
X0003Y0039
X0048
X0093
M30
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.apr 0 → 100644
View file @ 5aac9b06
D10 RECTANGULAR 90.551 84.646 0.000 FLASH 90.000
D11 RECTANGULAR 45.276 70.866 0.000 FLASH 270.000
D12 ROUNDED 39.370 39.370 0.000 LINE 0.000
D13 ROUNDED 10.000 10.000 0.000 LINE 0.000
D14 ROUNDED 118.110 118.110 0.000 FLASH 0.000
D15 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D16 ROUNDED 137.795 137.795 0.000 FLASH 0.000
D17 ROUNDED 39.370 39.370 0.000 FLASH 0.000
D18 ROUNDED 200.787 200.787 0.000 FLASH 0.000
D19 ROUNDED 7.874 7.874 0.000 LINE 0.000
D20 ROUNDED 9.842 9.842 0.000 LINE 0.000
D21 RECTANGULAR 98.551 92.646 0.000 FLASH 90.000
D22 RECTANGULAR 53.276 78.866 0.000 FLASH 270.000
D23 ROUNDED 126.110 126.110 0.000 FLASH 0.000
D24 ROUNDED 67.055 67.055 0.000 FLASH 0.000
D25 ROUNDED 145.795 145.795 0.000 FLASH 0.000
D26 ROUNDED 47.370 47.370 0.000 FLASH 0.000
D27 ROUNDED 208.787 208.787 0.000 FLASH 0.000
D28 ROUNDED 3.937 3.937 0.000 LINE 0.000
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/Status Report.Txt 0 → 100644
View file @ 5aac9b06
Output: Bill of Materials
Type : BOM
From : Variant [[No Variations]] of Project [RTM_Interface_Tester.PrjPCB]
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 10:21:06 AM On 7/1/2013
pcb/RTM_Interface_Tester/RTM_Interface_Tester.Dat 0 → 100644
View file @ 5aac9b06
Field=Description~String~Description~100|Field=Comment~String~Comment~100|Field=Designator~String~Designator~416|Field=Quantity~Integer~Quantity~100|ReportField=Currency~<none>|ReportField=ProductionQuantity~1|ReportField=ProjectFileName~RTM_Interface_Tester.PrjPCB|ReportField=ProjectFullPath~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.PrjPCB|ReportField=Title~Bill of Materials For Project [RTM_Interface_Tester.PrjPCB] (No PCB Document Selected)|ReportField=TotalQuantity~25|ReportField=ReportTime~10:21:21 AM|ReportField=ReportDate~7/1/2013|ReportField=ReportDateTime~7/1/2013 10:21:21 AM|ReportField=OutputName~Bill of Materials|ReportField=OutputType~BOM_PartType|ReportField=GeneratorName~BOM|ReportField=GeneratorDescription~Bill of Materials|ReportField=VariantName~None|ReportField=Address1~|ReportField=Address2~|ReportField=Address3~|ReportField=Address4~|ReportField=ApprovedBy~|ReportField=Author~|ReportField=CheckedBy~|ReportField=CheckedDate~-|ReportField=CompanyName~|ReportField=CreateDate~4/24/2013|ReportField=CurrentDate~7/1/2013|ReportField=CurrentTime~10:21:13 AM|ReportField=Date~|ReportField=Designer~Theodor-Adrian Stana|ReportField=DivGrp~BE/CO|ReportField=DocumentFullPathAndName~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.SchDoc|ReportField=DocumentName~RTM_Interface_Tester.SchDoc|ReportField=DocumentNumber~|ReportField=DrawnBy~Theodor-Adrian Stana|ReportField=EDA_Number~|ReportField=Engineer~Theodor-Adrian Stana|ReportField=ImagePath~|ReportField=ModifiedBy~-|ReportField=ModifiedDate~7/1/2013|ReportField=Organization~|ReportField=ProjectName~RTM_Interface_Tester.PrjPCB|ReportField=Projet~Blocking Pulse Repeater PTS|ReportField=Revision~|ReportField=Rule~|ReportField=SheetNumber~|ReportField=SheetTotal~|ReportField=Time~|ReportField=Title~PTS|ReportField=Title2~RTM Interface Tester|ReportField=DataSourceFileName~RTM_Interface_Tester.PrjPCB|ReportField=DataSourceFullPath~C:\Users\tstana\projects\conv-ttl-blo\pcb\RTM_Interface_Tester\RTM_Interface_Tester.PrjPCB
Resistor - 0.1%|51|R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18|18
Connector 160zabcd Female (5x32)|HAR-BUS 64|P2|1
Transient Voltage Suppressor Diode (Bi-Directional)|SMBJ30CA|D1, D2, D3, D4, D5, D6|6
pcb/RTM_Interface_Tester/RTM_Interface_Tester.OutJob 0 → 100644
View file @ 5aac9b06
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OutputPathOutputer4=[Output Type]
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pcb/RTM_Interface_Tester/RTM_Interface_Tester.PrjPCB 0 → 100644
View file @ 5aac9b06
This diff is collapsed.
pcb/RTM_Interface_Tester/RTM_Interface_Tester.PrjPCBStructure 0 → 100644
View file @ 5aac9b06
Record=TopLevelDocument|FileName=RTM_Interface_Tester.SchDoc
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