Commit 8aaf2d8f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

second draft of hdlguide and hwguide, additional info in userguide

parent 39d90872
......@@ -35,6 +35,14 @@
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{ctb-hwguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO Hardware Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/282}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
......
......@@ -41,6 +41,7 @@
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
\hline
\end{tabular}
}
......@@ -103,10 +104,11 @@ blocks in the figure is presented in following sections.
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
\textcolor{red}{\textbf{!!!}}
%\textcolor{red}{\textbf{!!!}}
\begin{itemize}
\item CONV-TTL-BLO User Guide \cite{ctb-ug}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\end{itemize}
%==============================================================================
......@@ -374,7 +376,7 @@ multiplexers are set throughout the logic.
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\
& \textcolor{red}{\textit{glitch\_filt\_en\_n}} & \textcolor{red}{Active-low glitch filter enable} \\
& \textit{glitch\_filt\_en\_n} & Active-low glitch filter enable \\
& \textit{trig\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~${\mu}s$ pulses \\
......@@ -504,12 +506,12 @@ The complete memory map of the firmware can be found in Appendix~\ref{app:memmap
\subsection{I$^2$C to Wishbone bridge}
\label{sec:elma-i2c}
The \textit{elma\_i2c} module \textcolor{red}{\textbf{REFERENCE}} implements a bridge between the serial lines on the
The \textit{elma\_i2c} module implements a bridge between the serial lines on the
VME P1 connector using the ELMA I$^2$C-based protocol~\cite{sysmon-i2c}, and the
Wishbone interconnect. The module provides one I$^2$C slave interface for connecting
to an ELMA SysMon and one Wishbone master interface.
Details about the module's implementation can be found in its documentation \textcolor{red}{\textbf{REFERENCE}}.
Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: CSR
......@@ -606,7 +608,7 @@ part of the CONV-TTL-BLO project are present in their own folders as sub-nodes o
\textit{conv-ttl-blo/hdl/} folder. In general, the module files are present under an
\textit{rtl/} sub-folder; documentation files (if any) for the modules appear under a
\textit{doc/} sub-folder. The I$^2$C bridge module folder also contains the instantiated
\textit{i2c\_slave.vhd} file (see \textcolor{red}{\textbf{REFERENCE TO ELMA\_I2C}}) and the documentation for it.
\textit{i2c\_slave} module and its documentation.
The \textit{release/} folder is the main folder in the firmware package, as can be seen from the
fact that it is bolded in the folder structure above. It contains top-level files in the
......@@ -629,7 +631,7 @@ VHDL, or net names that have been made clearer in VHDL code. Input ports are ass
signals and signals are assigned to output ports in each code section.
\begin{figure}[h]
\centerline{\includegraphics[scale=.8]{fig/declarative}}
\centerline{\includegraphics[scale=1]{fig/declarative}}
\caption{Declarative part of VHDL architecture}
\label{fig:declarative}
\end{figure}
......@@ -640,7 +642,7 @@ stant declarations, followed by component declarations, after which the var-
ious signals are declared.
\begin{figure}[h]
\centerline{\includegraphics[scale=.6]{fig/body}}
\centerline{\includegraphics[scale=1]{fig/body}}
\caption{Body of VHDL architecture}
\label{fig:body}
\end{figure}
......@@ -649,8 +651,10 @@ The body of the architecture is organised as shown in in Figure~\ref{fig:body}.
by instantiating a differential buffer for the 125~MHz system clock and instantiating the
\textit{reset\_gen} component. Then, the \textit{elma\_i2c} bridge module is instantiated
along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in
the design. Next, the CONV board CSR module is instantiated, followed by logic necessary
for each of the tests comprising PTS.
the design. Next, the CONV board CSR module is instantiated, followed by the instantiation
of twelve pulse generator modules, six for pulse repetition and six for the pulse LEDs.
This is followed by the logic for the status LEDs and the file ends with the RTM detection
modules.
%==============================================================================
......
......@@ -7,6 +7,14 @@
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{ctb-hdlguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO HDL Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/283}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
......@@ -67,3 +75,12 @@
title = {{High CMR, High Speed TTL Compatible Optocouplers}},
note = {\url{http://www.avagotech.com/docs/AV02-0940EN}}
}
@misc{nxp-an11158,
author = {{NXP Semiconductor}},
title = {{Understanding power MOSFET datasheet parameters}},
day = 7,
month = January,
year = 2013,
note = {\url{http://www.nxp.com/documents/application_note/AN11158.pdf}}
}
This diff is collapsed.
......@@ -46,3 +46,18 @@
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
}
@misc{ctb-hwguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO Hardware Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/282}}
}
@misc{ctb-hdlguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO HDL Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/283}}
}
......@@ -42,6 +42,7 @@
19-06-2013 & 1.00 & First version \\
21-06-2013 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\
22-07-2013 & 1.02 & New title page and page layout \\
26-07-2013 & 1.03 & Added additional documentation subsection \\
\hline
\end{tabular}
}
......@@ -128,6 +129,16 @@ pulse generation and conversion from/to blocking, as well as galvanic isolation
blocking outputs. CONV-TTL-RTM is a passive module used as an interface from the rear
part of the VME crate to the front module.
%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
\begin{itemize}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\item CONV-TTL-BLO HDL Guide \cite{ctb-hdlguide}
\end{itemize}
%======================================================================================
% SEC: Panels
%======================================================================================
......
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